- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1891 > AD6623ASZ (Analog Devices Inc)IC TSP 4CHAN 104MSPS 128MQFP PDF資料下載
參數(shù)資料
| 型號： | AD6623ASZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 19/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TSP 4CHAN 104MSPS 128MQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 應(yīng)用： | 傳輸信息處理器 |
| 接口： | 串行 |
| 封裝/外殼： | 128-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 128-MQFP（14x20） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁當(dāng)前第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁
REV. A
AD6623
–26–
Resampling is implemented by apparently increasing the input
sample rate by the factor L, using zero stuffing for the new data
samples. Following the resampler is a second order cascaded
integrator comb filter. Filter characteristics are determined only
by the fractional rate change (L/M).
The filter can produce output signals at the full CLK rate of
the AD6623. The output rate of this stage is given by the
equation below.
f
L
M
f
OUT
rCIC
=
2
(19)
Both LrCIC2 and MrCIC2 are unsigned integers. The interpolation
rate (LrCIC2) may be from 1 to 4096 and the decimation (MrCIC2)
may be between 1 and 512. The stage can be bypassed by setting
the L and M to 1.
The transfer function of the rCIC2 is given by the following
equations with respect to the rCIC2 output sample rate, fOUT.
rCIC
z
L
rCIC
2
1
2
1
2
()
–
=
(20)
Frequency Response of rCIC2
The frequency response of the rCIC2 can be expressed as
follows. The maximum gain is LrCIC2 at baseband. The initial
MrCIC2/LrCIC2 factor normalizes for the increased rate, which is
appropriate when the samples are destined for a DAC with a
zero order hold output.
rCIC
f
M
L
Lf
f
rCIC
out
2
()
=
×
sin
π
(21)
The pass-band droop of CIC5 should be calculated using this
equation and can be compensated for in the RCF stage. The
gain should be calculated from the CIC scaling section above.
Programming Guidelines for AD6623 CIC Filters
The values MrCIC2–1, LrCIC2–1 can be independently pro-
grammed for each channel at locations 0xn07, 0xn08. While
these control registers are nine bits and 12 bits wide respec-
tively, MrCIC2–1 and LrCIC2–1 should be confined to the ranges
shown by Table XIII according to the interpolation factor of the
CIC5. Exceeding the recommended guidelines may result in
overflow for input sequences at or near full scale. While rela-
tively large ratios of LrCIC2/MrCIC2 allow for the larger overall
interpolations with minimal power consumption, LrCIC2/MrCIC2
should be minimized to achieve the best overall image rejection.
As an example, consider an input from the CIC5 whose bandwidth
is 0.0033 of the CIC5 rate, centered at baseband. Interpolation
by a factor of five reveals five images, as shown below.
–150
–2
–1
dB
01
2
–130
–110
–90
–70
–50
–30
–10
10
–3
3
Figure 31. Unfiltered rCIC2 Images
The rCIC2 rejects each of the undesired images while passing
the image at baseband. The images of a pure tone at channel
center (DC) are nulled perfectly, but as the bandwidth increases
the rejection is diminished. The lower band edge of the first
image always has the least rejection. In this example, the rCIC2
is interpolating by a factor of five and the input signal has a
bandwidth of 0.0033 of the CIC5 output sample rate. Figure 32
shows –110 dBc rejection of the lower band edge of the first image.
All other image frequencies have better rejection.
10
dB
–10
–30
–3
3
–2
–1
0
1
2
–50
–70
–90
–110
–130
–150
Figure 32. Filtered rCIC2 Images
Table XIV lists maximum bandwidth that will be rejected to
various levels for CIC2 interpolation factors from 1 to 32. The
example above corresponds to the listing in the –110 dB column
and the LrCIC2 = 5 row. The rejection of the CIC2 improves as
the interpolation factor increases.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD6641BCPZRL7-500 | IC IF RCVR 11BIT 200MSPS 56LFCSP |
| AD664BJ | IC DAC 12BIT QUAD MONO 44-JLCC |
| AD667BD | IC DAC 12BIT W/BUFF LTCH 28-CDIP |
| AD669BN | IC DAC 16BIT MONO VREF 28-DIP |
| AD693AE | IC SGNL COND 4-20MA TX 20-CLCC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD6623BC/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, 104 MSPS Digital Transmit Signal Processor TSP |
| AD6623PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, 104 MSPS Digital Transmit Signal Processor TSP |
| AD6623S/PCB | 制造商:Analog Devices 功能描述:4-CH, 104 MSPS DGTL TRANSMIT SGNL PROCESSOR (TSP) 28SOIC - Bulk |
| AD6624 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Four-Channel, 80 MSPS Digital Receive Signal Processor (RSP) |
| AD6624A | 制造商:AD 制造商全稱:Analog Devices 功能描述:Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。