參數(shù)資料
型號： XCF128XFTG64C
廠商： Xilinx Inc
文件頁數(shù)： 67/88頁
文件大小： 0K
描述： IC PROM SRL 128M GATE 64-FTBGA
標(biāo)準(zhǔn)包裝： 1
可編程類型： 系統(tǒng)內(nèi)可編程
存儲容量： 128Mb
電源電壓： 1.7 V ~ 2 V
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-TBGA
供應(yīng)商設(shè)備封裝： 64-TFBGA
包裝： 托盤
產(chǎn)品目錄頁面： 601 (CN2011-ZH PDF)
其它名稱： 122-1578
Platform Flash XL High-Density Configuration and Storage Device
DS617 (v3.0.1) January 07, 2010
Product Specification
7
R
Latch Enable (L)
Latch Enable latches the address bits on its rising edge.
The address latch is transparent when Latch Enable is at
VIL and inhibited when Latch Enable is at VIH.
The Latch Enable (L) signal must be held at VIH during the
power-up phase, during the FALS restart phase and
through the entire FALS.
In asynchronous mode, the address is latched on L going
High. or addresses are sent continuously if L is held Low.
During Write operations, L can be tied Low (VIL) to allow the
addresses to flow through.
Clock (K)
The Clock input synchronizes the memory to the FPGA
during synchronous read operations. The address is
latched on a Clock edge (rising or falling, according to the
configuration settings) when Latch Enable is at VIL. Clock is
ignored during asynchronous read and in write operations.
Ready/Wait (READY_WAIT)
Caution! The READY_WAIT requires an external pull-up
resistor to VDDQ. The external pull-up resistor must be
sufficiently strong to ensure a clean, Low-to-High transition
within less than one microsecond (TRWRT) when the
READY_WAIT pin is released to a high-impedance state.
READY_WAIT can perform one of two functions. By default,
READY_WAIT is an input/open-drain ready signal
coordinating the initiation of the device's synchronous read
operation with the start of an FPGA configuration sequence.
Optionally, READY_WAIT can be dynamically configured as
an output wait signal, indicating a wait condition during a
synchronous read operation.
Upon a power-on reset (POR) or RP-pin reset event, the
device drives READY_WAIT to VIL until the device is ready to
initiate a synchronous read or receive a command. When the
device reaches an internal ready state from a reset condition,
READY_WAIT is released to a high-impedance state (an
external pull-up resistor to VDDQ is required to externally pull
the READY_WAIT signal to a valid input High). The device
waits until the READY_WAIT input becomes a valid input
High before permitting a synchronous read or accepting a
command. Connecting the READY_WAIT to the FPGA
INIT_B pin in a wired-and circuit creates a handshake
coordinating the initiation of the device synchronous read
with the start of the FPGA configuration sequence.
When READY_WAIT is an input/open-drain ready signal, the
system can drive READY_WAIT to VIL to reinitiate a
synchronous read operation. A valid address must be provided
to the device for a reinitiated synchronous read operation.
Optionally, READY_WAIT can be configured as an output
signaling a wait condition during a synchronous read
operation. The wait condition indicates a clock cycle during
which the output data is not valid. When configured as an
output wait signal, READY_WAIT is high impedance when
Chip Enable is at VIH or Output Enable is at VIH. Only when
configured as a wait signal, READY_WAIT can be configured
to be active during the wait cycle or one clock cycle in
advance, and the READY_WAIT polarity can be configured.
VDD Supply Voltage
VDD provides the power supply to the internal core of the
memory device and is the main power supply for all
operations (Read, Program and Erase).
VDDQ Supply Voltage
VDDQ provides the power supply to the I/O pins and enables
all outputs to be powered independently of VDD.
VPP Program Supply Voltage
VPP is either a control input or a power supply pin, selected
by the voltage range applied to the pin.
If VPP is kept in a low voltage range (0V to VDDQ), VPP is
seen as a control input. In this case a voltage lower than
VPPLK gives absolute protection against program or erase,
while VPP in the VPP1 range enables these functions. VPP is
only sampled at the beginning of a program or erase — a
change in its value after the operation starts does not have
any effect, and all program or erase operations continue.
If VPP is in the range of VPPH, the signal acts as a power
supply pin. In this condition VPP must be stable until the
Program/Erase algorithm is completed.
VSS Ground
VSS Ground is the reference for the core supply and must
be connected to the system ground.
VSSQ Ground
VSSQ Ground is the reference for the input/output circuitry
driven by VDDQ. VSSQ must be connected to VSS.
Note: Each device in a system should have VDD, VDDQ and VPP
decoupled with a 0.1
μF ceramic capacitor close to the pin (high-
frequency, inherently low-inductance capacitors should be placed
Table 3: Latch Enable Logic Levels in Synchronous
and Asynchronous Modes
Operation
Asynchronous
Synchronous
Bus Read
X
VIH
Bus Write
X or toggling
Address Latch
Toggling
Standby
X
Reset
VIH
FALS
VIH
Power-up
VIH
Notes:
1.
See waveforms in the "DC and AC Parameters" section for
details.
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