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| 型號： | XCF128XFTG64C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 62/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROM SRL 128M GATE 64-FTBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 存儲容量： | 128Mb |
| 電源電壓： | 1.7 V ~ 2 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 64-TBGA |
| 供應(yīng)商設(shè)備封裝： | 64-TFBGA |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 601 (CN2011-ZH PDF) |
| 其它名稱： | 122-1578 |
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Platform Flash XL High-Density Configuration and Storage Device
DS617 (v3.0.1) January 07, 2010
Product Specification
65
R
Table 40: Primary Algorithm-Specific Extended Query Table
Offset
Data
Description
Value
(P)h = 10Ah
0050h
0052h
0049h
Primary Algorithm extended Query table unique ASCII string “PRI”
"P"
R"
"I"
(P+3)h = 10Dh
0031h
Major version number, ASCII
"1"
(P+4)h = 10Eh
0033h
Minor version number, ASCII
"3"
(P+5)h = 10Fh
(P+7)h = 111h
(P+8)h = 112h
00E6h
0003h
0000h
Extended Query table contents for Primary Algorithm. Address (P+5)h contains
less significant byte:
bit 0 Chip Erase supported (1 = Yes, 0 = No)
bit 1 Erase Suspend supported (1 = Yes, 0 = No)
bit 2 Program Suspend supported (1 = Yes, 0 = No)
bit 3 Legacy Lock/Unlock supported (1 = Yes, 0 = No)
bit 4 Queued Erase supported (1 = Yes, 0 = No) \
bit 5 Instant individual block locking supported (1 = Yes, 0 = No)
bit 6 Protection bits supported (1 = Yes, 0 = No)
bit 7 Page mode read supported (1 = Yes, 0 = No)
bit 8 Synchronous read supported (1 = Yes, 0 = No)
bit 9 Simultaneous operation supported (1 = Yes, 0 = No)
bit 10 to 31 Reserved; undefined bits are ‘0’. If bit 31 is ‘1’ then another 31 bit
field of optional features follows at the end of the bit-30 field.
No
Yes
No
Yes
(P+9)h = 113h
0001h
Supported Functions after Suspend Read Array, Read Status Register and CFI
Query:
bit 0 Program supported after Erase Suspend (1 = Yes, 0 = No)
bit 7 to 1 Reserved; undefined bits are ‘0’
Yes
(P+A)h = 114h
(P+B)h = 115h
0003h
0000h
Block Protect Status Defines which bits in the Block Status Register section of
the Query are implemented:
bit 0 Block protect Status Register Lock/Unlock bit active (1 = Yes, 0 = No)
bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No)
bit 15 to 2; Reserved for future use undefined bits are ‘0’
Yes
(P+C)h = 116h
0018h
VDD Logic Supply Optimum Program/Erase voltage (highest performance):
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
1.8V
(P+D)h = 117h
0090h
VPP Supply Optimum Program/Erase voltage:
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
9V
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