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| 型號： | XCF128XFTG64C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 14/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROM SRL 128M GATE 64-FTBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 存儲(chǔ)容量： | 128Mb |
| 電源電壓： | 1.7 V ~ 2 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 64-TBGA |
| 供應(yīng)商設(shè)備封裝： | 64-TFBGA |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 601 (CN2011-ZH PDF) |
| 其它名稱： | 122-1578 |
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Platform Flash XL High-Density Configuration and Storage Device
DS617 (v3.0.1) January 07, 2010
Product Specification
21
R
Status Register
The Status Register provides information on the current or
previous program or erase operations. A Read Status
Register command is issued to read the contents of the
Status Register, refer to "Read Status Register Command,"
page 14 for more details. To output the contents, the Status
Register is latched and updated on the falling edge of the
Chip Enable or Output Enable signals and can be read until
Chip Enable or Output Enable returns to VIH.
The Status Register can only be read using single
asynchronous or synchronous reads. Bus Read operations
from any address within the bank always read the Status
Register during program and erase operations if no Read
Array command is issued.
The various bits convey information about the status and
any errors of the operation. Bits SR7, SR6, SR2 and SR0
give information on the status of the device and are set and
reset by the device. Bits SR5, SR4, SR3 and SR1 give
information on errors and are set by the device but must be
reset by issuing a Clear Status Register command or a
hardware reset.
If an error bit is set to ‘1’, the Status Register should be
reset before issuing another command.
The bits in the Status Register are summarized in Table 11.
Program/Erase Controller Status Bit (SR7)
The Program/Erase Controller Status bit indicates whether
the Program/Erase Controller is active or inactive in any
bank. When this bit is Low (set to ‘0’), the Program/Erase
Table 11: Status Register Bits
Bit
Name
Type
Logic
Level(1)
Definition
SR7
P/E.C. Status
Status
'1'
Ready
'0'
Busy
SR6
Erase Suspend Status
Status
'1'
Erase suspended
'0'
Erase In progress or completed
SR5
Erase/Blank Check
Status
Error
'1'
Erase/blank check error
'0'
Erase/blank check success
SR4
Program Status
Error
'1'
Program error
'0'
Program success
SR3
VPP Status
Error
'1'
VPP invalid, abort
'0'
VPP OK
SR2
Program Suspend
Status
'1'
Program suspended
'0'
Program In progress or completed
SR1
Block Protection Status
Error
'1'
Program/erase on protected block, abort
'0'
No operation to protected block
SR0
Bank Write Status
Status
'1'
SR7 = ‘1’
Not allowed
SR7 = ‘0’
Program or erase operation in a bank other
than the addressed bank
'0'
SR7 = ‘1’
No program or erase operation in the device
SR7 = ‘0’
Program or erase operation in addressed
bank
Multiple Word Program
Status (Buffer Enhanced
Factory Program mode)
Status
'1'
SR7 = ‘1’
Not allowed
SR7 = ‘0’
The device is NOT ready for the next Buffer
loading or is going to exit the BEFP mode
'0'
SR7 = ‘1’
The device has exited the BEFP mode
SR7 = ‘0’
The device is ready for the next Buffer
loading
Notes:
1.
Logic level '1' is High, '0' is Low.
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