參數(shù)資料
型號: XCF128XFTG64C
廠商: Xilinx Inc
文件頁數(shù): 48/88頁
文件大?。?/td> 0K
描述: IC PROM SRL 128M GATE 64-FTBGA
標準包裝: 1
可編程類型: 系統(tǒng)內(nèi)可編程
存儲容量: 128Mb
電源電壓: 1.7 V ~ 2 V
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TBGA
供應(yīng)商設(shè)備封裝: 64-TFBGA
包裝: 托盤
產(chǎn)品目錄頁面: 601 (CN2011-ZH PDF)
其它名稱: 122-1578
Platform Flash XL High-Density Configuration and Storage Device
DS617 (v3.0.1) January 07, 2010
Product Specification
52
R
X-Ref Target - Figure 30
Notes:
1.
The number of clock cycles to be inserted depends on the X latency set in the Configuration Register.
2.
The READY_ WAIT signal is configured to be active during wait state. READY_ WAIT signal is active Low.
3.
The CLOCK signal can be held High or Low.
4.
Address latched and data output on the rising clock edge. Either the rising or the falling edge of the clock signal, K, can be configured as the
active edge. Here, the active edge is the rising one.
5.
From the moment data is valid, soon after G becomes asserted, the READY_WAIT signal reverts its previous level.
Figure 30: Synchronous Burst Read Suspend AC Waveforms, CR4 = 0
DQ15–DQ0
E
G
A22–A0
L
READY_WAIT(2,5)
K(4)
VALID
VALID ADDRESS
T
LLLH
T
AVLH
T
AVKH
T
LLKH
T
ELKH
T
KHAX
VALID
Note 1
T
EHQX
T
EHQZ
T
GHQX
Hi-Z
T
ELTV
T
KHQV
T
EHTZ
T
GLQX
T
EHEL
T
GHQZ
T
GLQV
Note 3
Hi-Z
T
GLTV
T
GHTZ
High
W
DS617_24_053008
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