參數(shù)資料
型號(hào)： XCF128XFTG64C
廠商： Xilinx Inc
文件頁(yè)數(shù)： 45/88頁(yè)
文件大?。?/td> 0K
描述： IC PROM SRL 128M GATE 64-FTBGA
標(biāo)準(zhǔn)包裝： 1
可編程類型： 系統(tǒng)內(nèi)可編程
存儲(chǔ)容量： 128Mb
電源電壓： 1.7 V ~ 2 V
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-TBGA
供應(yīng)商設(shè)備封裝： 64-TFBGA
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 601 (CN2011-ZH PDF)
其它名稱： 122-1578
Platform Flash XL High-Density Configuration and Storage Device
DS617 (v3.0.1) January 07, 2010
Product Specification
5
R
Pinout and Signal Descriptions
See Figure 5 and Table 2 for a logic diagram and brief overview of the signals connected to this device.
Address Inputs (A22-A0)
The Address inputs select the words in the memory array to
access during Bus Read operations. During Bus Write
operations they control the commands sent to the
Command Interface of the Program/Erase Controller.
Data Inputs/Outputs (DQ15-DQ0)
The Data I/O output the data stored at the selected address
during a Bus Read operation or input a command or the
data to be programmed during a Bus Write operation.
Chip Enable (E)
The Chip Enable input activates the memory control logic,
input buffers, decoders and sense amplifiers. When Chip
Enable is at VIL and Reset is at VIH, the device is in active
mode. When Chip Enable is at VIH, the memory is
deselected, the outputs are high impedance, and the power
consumption is reduced to the standby level.
Output Enable (G)
The Output Enable input controls data outputs during the
Bus Read operation of the memory. Before the start of the
first address latching sequence (FALS), the Output Enable
input must be held Low before the clock starts toggling.
Write Enable (W)
The Write Enable input controls the Bus Write operation of
the memory’s Command Interface. The data and address
inputs are latched on the rising edge of Chip Enable or
Write Enable, whichever occurs first.
Table 2: Signal Names
Signal Name
Function
Direction
A22-A0
Address Inputs
Inputs
DQ15-DQ0
Data Input/Outputs,
Command Inputs
I/O
E
Chip Enable
Input
G
Output Enable
Input
W
Write Enable
Input
RP
Reset
Input
WP
Write Protect
Input
K
Clock
Input
L
Latch Enable
Input
READY_WAIT
Ready/Wait
I/O
VDD
Supply Voltage
–
VDDQ
Supply Voltage for
Input/Output Buffers
–
VPP
Optional(1) Supply
Voltage for Fast
Program and Erase
–
VSS
Ground
–
VSSQ
Ground Input/output
Supply
–
NC
Not Connected
Internally
–
Notes:
1.
Typically, VPP is tied to the VDDQ supply on a board. See the VPP
Program Supply Voltage section for alternate options.
X-Ref Target - Figure 5
Figure 5: Logic Diagram
Platform
Flash XL
READY_WAIT
A22–A0
W
K
VSS
VSSQ
VDD
VDDQ
VPP
DQ15–DQ0
16
E
G
RP
WP
L
DS617_05_053008
23
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