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參數(shù)資料
| 型號： | XCF128XFTG64C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 33/88頁 |
| 文件大小： | 0K |
| 描述： | IC PROM SRL 128M GATE 64-FTBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 存儲容量： | 128Mb |
| 電源電壓： | 1.7 V ~ 2 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 64-TBGA |
| 供應(yīng)商設(shè)備封裝： | 64-TFBGA |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 601 (CN2011-ZH PDF) |
| 其它名稱： | 122-1578 |
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Platform Flash XL High-Density Configuration and Storage Device
DS617 (v3.0.1) January 07, 2010
Product Specification
39
R
First Address Latching Sequence
The first address latching sequence (FALS) is one of the key
features of Platform Flash XL. This particular sequence,
shown in Figure 19, page 41 and Figure 21, page 43,
allows the device to latch the first address soon after VIH is
detected on the READY_WAIT pin.
FALS requires four clock cycles. The device internally
latches the address from which the system must start to
read on the third detected positive edge of the clock after
READY_WAIT goes High.
In the case of a system with a free-running clock, FALS
takes place in the same way, but it is strongly recommended
(see Note 3) to use the timings represented in Figure 12,
page 31, Figure 14, page 32, Figure 16, page 33 and
Figure 17, page 39.
To start the sequence, the following conditions must be met
at the same time:
L must be tied High.
RP must be tied High.
G must be held Low (see Note 2).
FALS is always reset when READY_WAIT is asserted Low,
and CR4 is set to 1.
The major advantage of this feature is that it allows the
system to start reading data from any available main
memory address in the device. If the system cannot
guarantee any of the timings, the data output from the
device is not guaranteed.
Notes:
1.
If VDDQ drops, the output is no longer guaranteed, and it is
necessary to reset the device by performing an external reset.
2.
Only on power-on-reset, FALS is initiated by READY_WAIT rising
(Low-to-High) edge or G falling (High-to-Low) edge, whichever
occurs last. After POR, FALS is initiated only by a READY_WAIT
rising edge.
3.
Due to the internal threshold of the READY_WAIT signal, the
system might not exactly determine which of the clock edges are
the right ones to perform the sequence in the right way.
X-Ref Target - Figure 19
Notes:
1.
W is tied High.
Figure 19: First Address Latching Sequence (FALS)
Clock is not Free Running and G is Held Low
K
VDD/VDDQ
Address not Valid
A22–A0
First Address
FFFFh (Sync + Dummy Cycle)
DQ15–DQ0
READY_WAIT
First Address Latching Sequence
G
DS617_15_102308
High
RP
E
Low
T
RWHKH
T
RWHKL
T
KH3AX
T
AVKH3
L
123
4
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