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| 型號(hào)： | XCF128XFTG64C |
| 廠(chǎng)商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 19/88頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PROM SRL 128M GATE 64-FTBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 可編程類(lèi)型： | 系統(tǒng)內(nèi)可編程 |
| 存儲(chǔ)容量： | 128Mb |
| 電源電壓： | 1.7 V ~ 2 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 64-TBGA |
| 供應(yīng)商設(shè)備封裝： | 64-TFBGA |
| 包裝： | 托盤(pán) |
| 產(chǎn)品目錄頁(yè)面： | 601 (CN2011-ZH PDF) |
| 其它名稱(chēng)： | 122-1578 |
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Platform Flash XL High-Density Configuration and Storage Device
DS617 (v3.0.1) January 07, 2010
Product Specification
26
R
Wrap Burst Bit (CR3)
The Wrap Burst bit (CR3) is used to select between wrap
and no wrap. Synchronous burst reads can be confined
inside the 4, 8 or 16-word boundary (wrap) or overcome the
boundary (no wrap). When this bit is Low (set to ‘0’), the
burst read wraps. When it is High (set to ‘1’), the burst read
does not wrap.
Burst Length Bits (CR2-CR0)
The Burst Length bits are used to set the number of words
to be output during a Synchronous Burst Read operation as
result of a single address latch cycle. These bits can be set
for 4 words, 8 words, 16 words or continuous burst, where
all the words are read sequentially. In continuous burst
mode, the burst sequence can cross bank boundaries.
In continuous burst mode, or 4, 8 or 16 words no-wrap,
depending on the starting address, the device asserts the
WAIT signal to indicate that a delay is necessary before the
data is output.
If the starting address is shifted by 1, 2 or 3 positions from
the four-word boundary, WAIT is asserted for 1, 2 or 3 clock
cycles, respectively, when the burst sequence crosses the
first 16-word boundary, to indicate that the device needs an
internal delay to read the successive words in the array.
WAIT is asserted only once during a continuous burst
access. See also Table 14, page 29.
CR14 and CR5 are reserved for future use.
X-Ref Target - Figure 9
Figure 9: X-Latency and Data Output Configuration Example
A22–A0
VALID ADDRESS
K
L
DQ15–DQ0
VALID DATA
X-latency
VALID DATA
T
ACC
T
AVK_CPU
T
K
T
QVK_CPU
T
QVK_CPU
T
KQV
1st cycle
2nd cycle
3rd cycle
4th cycle
E
T
DELAY
DS617_42_032508
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCF128XFTG64CES | 制造商:Xilinx 功能描述: |
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