參數(shù)資料
型號： XCF128XFTG64C
廠商： Xilinx Inc
文件頁數(shù)： 64/88頁
文件大小： 0K
描述： IC PROM SRL 128M GATE 64-FTBGA
標(biāo)準(zhǔn)包裝： 1
可編程類型： 系統(tǒng)內(nèi)可編程
存儲容量： 128Mb
電源電壓： 1.7 V ~ 2 V
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-TBGA
供應(yīng)商設(shè)備封裝： 64-TFBGA
包裝： 托盤
產(chǎn)品目錄頁面： 601 (CN2011-ZH PDF)
其它名稱： 122-1578
Platform Flash XL High-Density Configuration and Storage Device
DS617 (v3.0.1) January 07, 2010
Product Specification
67
R
Table 44: Bank and Erase Block Region 1 Information(1,2)
Offset
Data
Description
(P+24)h = 12Eh
0Fh
Number of identical banks within Bank Region 1
(P+25)h = 12Fh
00h
(P+26)h = 130h
11h
Number of program or erase operations allowed in Bank Region 1:
Bits 0–3: Number of simultaneous program operations Bits
4–7: Number of simultaneous erase operations
(P+27)h = 131h
00h
Number of program or erase operations allowed in other banks while a bank in same region is
programming
Bits 0–3: Number of simultaneous program operations
Bits 4–7: Number of simultaneous erase operations
(P+28)h = 132h
00h
Number of program or erase operations allowed in other banks while a bank in this region is
erasing
Bits 0–3: Number of simultaneous program operations Bits
4–7: Number of simultaneous erase operations
(P+29)h = 133h
01h
Types of erase block regions in Bank Region 1 n = number of erase block regions with
contiguous same-sized erase blocks. Symmetrically blocked banks have one blocking
region(2).
(P+2A)h = 134h
07h
Bank Region 1 Erase Block Type 1 Information:
Bits 0–15: n+1 = number of identical-sized erase blocks
Bits 16–31: n×256 = number of bytes in erase block region
(P+2B)h = 135h
00h
(P+2C)h = 136h
00h
(P+2D)h = 137h
02h
(P+2E)h = 138h
64h
Bank Region 1 (Erase Block Type 1)
Minimum block erase cycles × 1000
(P+2F)h = 139h
00h
(P+30)h = 13Ah
01h
Bank Region 1 (Erase Block Type 1): BIts per cell, internal ECC
Bits 0–3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
BIts 5–7: reserved
(P+31)h = 13Bh
03h
Bank Region 1 (Erase Block Type 1): Page mode and Synchronous mode capabilities
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3–7: reserved
––
Bank Region 1 Erase Block Type 2 Information
Bits 0–15: n+1 = number of identical-sized erase blocks
Bits 16–31: n×256 = number of bytes in erase block region
Bank Region 1 (Erase Block Type 2)
Minimum block erase cycles × 1000
Bank Regions 1 (Erase Block Type 2): Bits per cell, internal ECC
Bits 0–3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
Bits 5–7: reserved
Bank Region 1 (Erase Block Type 2): Page mode and Synchronous mode capabilities
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3–7: reserved
Notes:
1.
The variable P is a pointer which is defined at CFI offset 015h.
2.
Bank Regions. There are two Bank Regions, see Table 35, page 61.
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