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Chapter 13 FlexRay Communication Controller (FLEXRAY)
MC9S12XF - Family Reference Manual, Rev.1.19
Freescale Semiconductor
543
13.6.3.2
Receive Shadow Buffers
The receive shadow buffers are required for the frame reception process for individual message buffers.
The FlexRay block provides four receive shadow buffers, one receive shadow buffer per channel and per
message buffer segment.
Each receive shadow buffer consists of two parts, the physical message buffer located in the FRM and the
receive shadow buffer control registers located in dedicated registers. The structure of a receive shadow
buffer is shown in
Figure 13-102. The four internal shadow buffer control registers can be accessed by the
The connection between the receive shadow buffer control register and the physical message buffer for the
selected receive shadow buffer is established by the receive shadow buffer index eld RSBIDX in the
buffer header eld in the FRM is determined according to
Equation 13-4.
SADR_MBHF = (RSBIR[RSBIDX] * 10) + SYS_MEM_BASE_ADDR
Eqn. 13-4
The length required for the message buffer data eld depends on the message buffer segment that the
receive shadow buffer is assigned to. For the receive shadow buffers assigned to the rst message buffer
segment, the length must be the same as for the individual message buffers assigned to the rst message
buffer segment. For the receive shadow buffers assigned to the second message buffer segment, the length
must be the same as for the individual message buffers assigned to the second message buffer segment.
Figure 13-102. Receive Shadow Buffer Structure
13.6.3.3
Receive FIFO
The receive FIFO implements a frame reception system based on the FIFO concept. The FlexRay block
provides two independent receive FIFOs, one per channel.
A receive FIFO consists of a set of physical message buffers in the FRM and a set of receive FIFO control
registers located in dedicated registers. The structure of a receive FIFO is given in
Figure 13-103.RSBIDX[3]
RSBIDX[2]
RSBIDX[1]
RSBIDX[0]
Receive Shadow Buffer Control Register
(min) MBDSR[MBSEG1DS] * 2 bytes / MBDSR[MBSEG2DS] * 2 bytes
Data Field Offset
Frame Data
Message Buffer Header Field
Message Buffer Data Field
Slot Status
Frame Header
SADR_MBDF
SADR_MBHF
System
Memor
y