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Chapter 21 Freescale’s Scalable Controller Area Network (S12MSCANV2)
MC9S12XF - Family Reference Manual, Rev.1.19
980
Freescale Semiconductor
21.3.2.17 MSCAN Identier Mask Registers (CANIDMR0–CANIDMR7)
The identier mask register species which of the corresponding bits in the identier acceptance register
are relevant for acceptance ltering. To receive standard identiers in 32 bit lter mode, it is required to
program the last three bits (AM[2:0]) in the mask registers CANIDMR1 and CANIDMR5 to “don’t care.”
To receive standard identiers in 16 bit lter mode, it is required to program the last three bits (AM[2:0])
in the mask registers CANIDMR1, CANIDMR3, CANIDMR5, and CANIDMR7 to “don’t care.”
Table 21-21. CANIDAR0–CANIDAR3 Register Field Descriptions
Field
Description
7-0
AC[7:0]
Acceptance Code Bits — AC[7:0] comprise a user-dened sequence of bits with which the corresponding bits
of the related identier register (IDRn) of the receive message buffer are compared. The result of this comparison
is then masked with the corresponding identier mask register.
Module Base + 0x0018 to Module Base + 0x001B
Access: User read/write(1)
1. Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
76543210
R
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
W
Reset
00000000
Figure 21-20. MSCAN Identier Acceptance Registers (Second Bank) — CANIDAR4–CANIDAR7
Table 21-22. CANIDAR4–CANIDAR7 Register Field Descriptions
Field
Description
7-0
AC[7:0]
Acceptance Code Bits — AC[7:0] comprise a user-dened sequence of bits with which the corresponding bits
of the related identier register (IDRn) of the receive message buffer are compared. The result of this comparison
is then masked with the corresponding identier mask register.
Module Base + 0x0014 to Module Base + 0x0017
Access: User read/write(1)
1. Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
76543210
R
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
W
Reset
00000000
Figure 21-21. MSCAN Identier Mask Registers (First Bank) — CANIDMR0–CANIDMR3