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Chapter 20 Pulse Width Modulator with Fault Protection (PMF15B6C) Module
MC9S12XF - Family Reference Manual, Rev.1.19
938
Freescale Semiconductor
NOTE
The waveform at the pad is delayed by two bus clock cycles for deadtime
insertion.
20.4.5.1
Top/Bottom Correction
In complementary mode, either the top or the bottom transistor controls the output voltage. However,
deadtime has to be inserted to avoid overlap of conducting interval between the top and bottom transistor.
Both transistors in complementary mode are off during deadtime, allowing the output voltage to be
determined by the current status of load and introduce distortion in the output voltage. See
Figure 20-53.
On AC induction motors running open-loop, the distortion typically manifests itself as poor low-speed
performance, such as torque ripple and rough operation.
Figure 20-53. Deadtime Distortion
During deadtime, load inductance distorts output voltage by keeping current owing through the diodes.
This deadtime current ow creates a load voltage that varies with current direction. With a positive current
ow, the load voltage during deadtime is equal to the bottom supply, putting the top transistor in control.
With a negative current ow, the load voltage during deadtime is equal to the top supply putting the bottom
transistor in control.
Remembering that the original PWM pulse widths were shortened by deadtime insertion, the averaged
sinusoidal output will be less than desired value. However, when deadtime is inserted, it creates a distortion
in motor current waveform. This distortion is aggravated by dissimilar turn-on and turn-off delays of each
of the transistors. By giving the PWM module information on which transistor is controlling at a given
time this distortion can be corrected.
For a typical circuit in complementary channel operation, only one of the transistors will be effective in
controlling the output voltage at any given time. This depends on the direction of the motor current for that
pair. See
Figure 20-53. To correct distortion one of two different factors must be added to the desired PWM
value, depending on whether the top or bottom transistor is controlling the output voltage. Therefore, the
DESIRED
DEADTIME
PWM TO TOP
POSITIVE
NEGATIVE
PWM TO BOTTOM
POSITIVE CURRENT
NEGATIVE CURRENT
LOAD VOLTAGE
TRANSISTOR
LOAD VOLTAGE
CURRENT
V+