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Chapter 21 Freescale’s Scalable Controller Area Network (S12MSCANV2)
MC9S12XF - Family Reference Manual, Rev.1.19
Freescale Semiconductor
967
21.3.2.3
MSCAN Bus Timing Register 0 (CANBTR0)
The CANBTR0 register congures various CAN bus timing parameters of the MSCAN module.
1
SLPAK
Sleep Mode Acknowledge — This ag indicates whether the MSCAN module has entered sleep mode (see
Sleep mode is active when SLPRQ = 1 and SLPAK = 1. Depending on the setting of WUPE, the MSCAN will
clear the ag if it detects activity on the CAN bus while in sleep mode.
0 Running — The MSCAN operates normally
1 Sleep mode active — The MSCAN has entered sleep mode
0
INITAK
Initialization Mode Acknowledge — This ag indicates whether the MSCAN module is in initialization mode
mode request. Initialization mode is active when INITRQ = 1 and INITAK = 1. The registers CANCTL1,
CANBTR0, CANBTR1, CANIDAC, CANIDAR0–CANIDAR7, and CANIDMR0–CANIDMR7 can be written only by
the CPU when the MSCAN is in initialization mode.
0 Running — The MSCAN operates normally
1 Initialization mode active — The MSCAN has entered initialization mode
Module Base + 0x0002
Access: User read/write(1)
1. Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
76543210
R
SJW1
SJW0
BRP5
BRP4
BRP3
BRP2
BRP1
BRP0
W
Reset:
00000000
Figure 21-6. MSCAN Bus Timing Register 0 (CANBTR0)
Table 21-5. CANBTR0 Register Field Descriptions
Field
Description
7-6
SJW[1:0]
Synchronization Jump Width — The synchronization jump width denes the maximum number of time quanta
(Tq) clock cycles a bit can be shortened or lengthened to achieve resynchronization to data transitions on the
5-0
BRP[5:0]
Baud Rate Prescaler — These bits determine the time quanta (Tq) clock which is used to build up the bit timing
Table 21-6. Synchronization Jump Width
SJW1
SJW0
Synchronization Jump Width
0
1 Tq clock cycle
0
1
2 Tq clock cycles
1
0
3 Tq clock cycles
1
4 Tq clock cycles
Table 21-4. CANCTL1 Register Field Descriptions (continued)
Field
Description