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Chapter 19 Port Integration Module (S12XFPIMV2)
MC9S12XF - Family Reference Manual, Rev.1.19
862
Freescale Semiconductor
19.3.21 Port T Data Register (PTT)
19.3.22 Port T Input Register (PTIT)
Address 0x0240
Access: User read/write(1)
1. Read: Anytime.
Write: Anytime.
76543210
R
PTT7
PTT6
PTT5
PTT4
PTT3
PTT2
PTT1
PTT0
W
Altern.
Function
IOC7
IOC6
IOC5
IOC4
IOC3
IOC2
IOC1
IOC0
—
VREG_API
—————
Reset
00000000
Figure 19-19. Port T Data Register (PTT)
Table 19-20. PTT Register Field Descriptions
Field
Description
7-6
PTT
Port T general purpose input/output data—Data Register
Port T pins 7 through 0 are associated with ECT channels IOC7 and IOC6.
When not used with the alternative function, these pins can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
5
PTT
Port T general purpose input/output data—Data Register
Port T pins 5 is associated with ECT channel IOC5 and the VREG_API output.
The ECT function takes precedence over the VREG_API and the general purpose I/O function if the related channel
is enabled.
When not used with the alternative function, these pins can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
4-0
PTT
Port T general purpose input/output data—Data Register
Port T pins 4 through 0 are associated with ECT channels IOC4 through IOC0.
When not used with the alternative function, these pins can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Address 0x0241
Access: User read/write(1)
76543210
R
PTIT7
PTIT6
PTIT5
PTIT4
PTIT3
PTIT2
PTIT1
PTIT0
W
Reset
uuuuuuuu
= Unimplemented or Reserved
u = Unaffected by reset
Figure 19-20. Port T Input Register (PTIT)