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Chapter 13 FlexRay Communication Controller (FLEXRAY)
MC9S12XF - Family Reference Manual, Rev.1.19
480
Freescale Semiconductor
13.5.2.11 Global Interrupt Flag and Enable Register (GIFER)
7
BSY
WMC
Protocol Control Command Write Busy — This status bit indicates the acceptance of the protocol control
command issued by the application via the POCCMD eld. The FlexRay block sets this status bit when the
application has issued a protocol control command via the POCCMD eld. The FlexRay block clears this status
bit when protocol control command was accepted by the PE.When the application issues a protocol control
command while the BSY bit is asserted, the FlexRay block ignores this command, sets the protocol command
POCCMD eld.
0 Command write idle, command accepted and ready to receive new protocol command.
1 Command write busy, command not yet accepted, not ready to receive new protocol command.
Write Mode Command — This bit controls the write mode of the POCCMD eld.
0 Write to POCCMD eld on register write.
1 Do not write to POCCMD eld on register write.
3–0
POCCMD
Protocol Control Command — The application writes to this eld to issue a protocol control command to the
PE. The FlexRay block sends the protocol command to the PE immediately. While the transfer is running, the
BSY bit is set.
0000 ALLOW_COLDSTART — Immediately activate capability of node to cold start cluster.
0001 ALL_SLOTS — Delayed(1) transition to the all slots transmission mode.
0010 CONFIG — Immediately transition to the POC:cong state.
0011 FREEZE — Immediately transition to the POC:halt state.
0100 READY, CONFIG_COMPLETE — Immediately transition to the POC:ready state.
0101 RUN — Immediately transition to the POC:startup start state.
0110 DEFAULT_CONFIG — Immediately transition to the POC:default cong state.
0111 HALT — Delayed transition to the POC:halt state
1000 WAKEUP — Immediately initiate the wakeup procedure.
1001 reserved
1010 reserved
1011 reserved
1100 RESET(2) — Immediately reset the Protocol Engine.
1101 reserved
1110 reserved
1111 reserved
1. Delayed means on completion of current communication cycle.
After sending the RESET command, it is mandatory to execute the
Command” immediately, to reach the DEFAULT CONFIG state correctly.
Module Base + 0x0016
15
14
13
12
11
10
9876543210
R
MIF
PRIF
CHIF
WUP
IF
FNEB
IF
FNEA
IF
RBIF
TBIF
MIE
PRIE
CHIE
WUP
IE
FNEB
IE
FNEA
IE
RBIE
TBIE
W
w1c
Reset
0000000000000000
Figure 13-11. Global Interrupt Flag and Enable Register (GIFER)
Table 13-17. POCR Field Descriptions (Sheet 2 of 2)
Field
Description