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參數(shù)資料
| 型號： | S29WS128N0LBFW010 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 256/128/64 MEGABIT CMOS 1.8 VOLT ONLY SIMULTANEOUS READ/WRITE BURST MODE FLASH MEMORY |
| 中文描述： | 8M X 16 FLASH 1.8V PROM, 70 ns, PBGA84 |
| 封裝： | 11.60 X 8 MM, LEAD FREE, PLASTIC, FBGA-84 |
| 文件頁數(shù)： | 77/95頁 |
| 文件大?。?/td> | 1745K |
| 代理商： | S29WS128N0LBFW010 |
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October 29, 2004 S29WSxxxN_00_F0
79
Pre l i m i n a r y
Notes:
1. RDY(1) active with data (D8 = 1 in the Configuration Register).
2. RDY(2) active one clock cycle before data (D8 = 0 in the Configuration Register).
3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60.
4. Figure shows the device not crossing a bank in the process of performing an erase or program.
5. RDY will not go low and no additional wait states will be required if the Burst frequency is <=66 MHz and the Boundary Crossing bit (D14)
in the Configuration Register is set to 0
Figure 11.20. Latency with Boundary Crossing when Frequency > 66 MHz
Enter
Erase
Enter Erase
Suspend Program
Erase Suspend
Read
Erase Suspend
Read
Erase
WE#
DQ6
DQ2
Erase
Complete
Erase
Suspend
Program
Resume
Embedded
Erasing
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE#
to toggle DQ2 and DQ6.
Figure 11.19. DQ2 vs. DQ6
CLK
Address (hex)
C124
C125
C126
C127
C128
C129
C130
C131
D124
D125
D126
D127
D128
D129
D130
(stays high)
AVD#
RDY(1)
Data
OE#,
CE#
(stays low)
Address boundary occurs every 128 words, beginning at address
00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.
7C
7D
7E
7F
80
81
82
83
latency
RDY(2)
latency
tRACC
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