參數(shù)資料
型號： S29WS128N0LBFW010
廠商： SPANSION LLC
元件分類： PROM
英文描述： 256/128/64 MEGABIT CMOS 1.8 VOLT ONLY SIMULTANEOUS READ/WRITE BURST MODE FLASH MEMORY
中文描述： 8M X 16 FLASH 1.8V PROM, 70 ns, PBGA84
封裝： 11.60 X 8 MM, LEAD FREE, PLASTIC, FBGA-84
文件頁數(shù)： 13/95頁
文件大?。?/td> 1745K
代理商： S29WS128N0LBFW010
20
S29WSxxxN_00_F0 October 29, 2004
Pr e l i m i n a r y
access time (tCE) is the delay from the stable CE# to valid data at the outputs. The output
enable access time (tOE) is the delay from the falling edge of OE# to valid data at the output.
7.3 Synchronous (Burst) Read Mode &
Configuration Register
When a series of adjacent addresses needs to be read from the device (in order from lowest
to highest address), the synchronous (or burst read) mode can be used to significantly reduce
the overall time needed for the device to output array data. After an initial access time re-
quired for the data from the first address location, subsequent data is output synchronized to
a clock input provided by the system.
The device offers both continuous and linear methods of burst read operation, which are dis-
cussed in subsections 7.3.1 and 7.3.2, and 7.3.3.
Since the device defaults to asynchronous read mode after power-up or a hardware reset, the
configuration register must be set to enable the burst read mode. Other Configuration Regis-
ter settings include the number of wait states to insert before the initial word (tIACC) of each
burst access, the burst mode in which to operate, and when RDY will indicate data is ready
to be read. Prior to entering the burst mode, the system should first determine the configu-
ration register settings (and read the current register settings if desired via the Read
Configuration Register command sequence), and then write the configuration register com-
Commands for further details.
Figure 7.1. Synchronous/Asynchronous State Diagram
The device outputs the initial word subject to the following operational conditions:
tIACC specification: the time from the rising edge of the first clock cycle after addresses
are latched to valid data on the device outputs.
configuration register setting CR13–CR11: the total number of clock cycles (wait states)
that occur before valid data appears on the device outputs. The effect is that tIACC is
lengthened.
Power-up/
Hardware Reset
Asynchronous Read
Mode Only
Synchronous Read
Mode Only
Set Burst Mode
Configuration Register
Command for
Synchronous Mode
(CR15 = 0)
Set Burst Mode
Configuration Register
Command for
Asynchronous Mode
(CR15 = 1)
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