參數(shù)資料
型號(hào)： S29WS128N0LBFW010
廠商： SPANSION LLC
元件分類： PROM
英文描述： 256/128/64 MEGABIT CMOS 1.8 VOLT ONLY SIMULTANEOUS READ/WRITE BURST MODE FLASH MEMORY
中文描述： 8M X 16 FLASH 1.8V PROM, 70 ns, PBGA84
封裝： 11.60 X 8 MM, LEAD FREE, PLASTIC, FBGA-84
文件頁數(shù)： 31/95頁
文件大?。?/td> 1745K
代理商： S29WS128N0LBFW010
October 29, 2004 S29WSxxxN_00_F0
37
Pre l i m i n a r y
7.5.4 Chip Erase Command Sequence
Chip erase is a six-bus cycle operation as indicated by Table 12.1. These commands invoke
the Embedded Erase algorithm, which does not require the system to preprogram prior to
erase. The Embedded Erase algorithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical erase. The system is not required to
provide any controls or timings during these operations. The “Command Definition” section
in the appendix shows the address and data requirements for the chip erase command
sequence.
When the Embedded Erase algorithm is complete, that bank returns to the read mode and
addresses are no longer latched. The system can determine the status of the erase operation
by using DQ7 or DQ6/DQ2. Refer to “Write Operation Status” for information on these status
bits.
Any commands written during the chip erase operation are ignored. However, note that a
hardware reset immediately terminates the erase operation. If that occurs, the chip erase
command sequence should be reinitiated once that bank has returned to reading array data,
to ensure data integrity.
The following is a C source code example of using the chip erase function. Refer to the Span-
sion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com) for
general information on Spansion Flash memory software development guidelines.
/* Example: Chip Erase Command */
/* Note: Cannot be suspended
*/
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
/* write unlock cycle 1
*/
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
/* write unlock cycle 2
*/
*( (UINT16 *)base_addr + 0x555 ) = 0x0080;
/* write setup command
*/
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
/* write additional unlock cycle 1 */
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
/* write additional unlock cycle 2 */
*( (UINT16 *)base_addr + 0x000 ) = 0x0010;
/* write chip erase command
*/
7.5.5 Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt a sector erase operation and
then read data from, or program data to, any sector not selected for erasure. The bank ad-
dress is required when writing this command. This command is valid only during the sector
erase operation, including the minimum tSEA time-out period during the sector erase com-
mand sequence. The Erase Suspend command is ignored if written during the chip erase
operation.
When the Erase Suspend command is written during the sector erase operation, the device
requires a maximum of tESL (erase suspend latency) to suspend the erase operation. How-
Software Functions and Sample Code
Table 7.25. Chip Erase
(LLD Function = lld_ChipEraseCmd)
Cycle
Description
Operation
Byte Address
Word Address
Data
1
Unlock
Write
Base + AAAh
Base + 555h
00AAh
2
Unlock
Write
Base + 554h
Base + 2AAh
0055h
3
Setup Command
Write
Base + AAAh
Base + 555h
0080h
4
Unlock
Write
Base + AAAh
Base + 555h
00AAh
5
Unlock
Write
Base + 554h
Base + 2AAh
0055h
6
Chip Erase Command
Write
Base + AAAh
Base + 555h
0010h
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