參數(shù)資料
型號： S29WS128N0LBFW010
廠商： SPANSION LLC
元件分類： PROM
英文描述： 256/128/64 MEGABIT CMOS 1.8 VOLT ONLY SIMULTANEOUS READ/WRITE BURST MODE FLASH MEMORY
中文描述： 8M X 16 FLASH 1.8V PROM, 70 ns, PBGA84
封裝： 11.60 X 8 MM, LEAD FREE, PLASTIC, FBGA-84
文件頁數(shù)： 36/95頁
文件大?。?/td> 1745K
代理商： S29WS128N0LBFW010
October 29, 2004 S29WSxxxN_00_F0
41
Pre l i m i n a r y
/* Example: Unlock Bypass Program Command
*/
/* Do while in Unlock Bypass Entry Mode!
*/
*( (UINT16 *)bank_addr + 0x555 ) = 0x00A0;
/* write program setup command
*/
*( (UINT16 *)pa )
= data;
/* write data to be programmed
*/
/* Poll until done or error.
*/
/* If done and more to program, */
/* do above two cycles again.
*/
/* Example: Unlock Bypass Exit Command */
*( (UINT16 *)base_addr + 0x000 ) = 0x0090;
*( (UINT16 *)base_addr + 0x000 ) = 0x0000;
7.5.9 Write Operation Status
The device provides several bits to determine the status of a program or erase operation. The
following subsections describe the function of DQ1, DQ2, DQ3, DQ5, DQ6, and DQ7.
DQ7: Data# Polling.
The Data# Polling bit, DQ7, indicates to the host system whether an
Embedded Program or Erase algorithm is in progress or completed, or whether a bank is in
Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the com-
mand sequence. Note that the Data# Polling is valid only for the last word being programmed
in the write-buffer-page during Write Buffer Programming. Reading Data# Polling status on
any word other than the last word to be programmed in the write-buffer-page will return false
status information.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the
datum programmed to DQ7. This DQ7 status also applies to programming during Erase Sus-
pend. When the Embedded Program algorithm is complete, the device outputs the datum
programmed to DQ7. The system must provide the program address to read valid status in-
formation on DQ7. If a program address falls within a protected sector, Data# polling on DQ7
is active for approximately tPSP, then that bank returns to the read mode.
During the Embedded Erase Algorithm, Data# polling produces a “0” on DQ7. When the Em-
bedded Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data#
Polling produces a “1” on DQ7. The system must provide an address within any of the sectors
selected for erasure to read valid status information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected,
Data# Polling on DQ7 is active for approximately tASP, then the bank returns to the read
mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the un-
protected sectors, and ignores the selected sectors that are protected. However, if the system
reads DQ7 at an address within a protected sector, the status may not be valid.
Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change
asynchronously with DQ6-DQ0 while Output Enable (OE#) is asserted low. That is, the device
may change from providing status information to valid data on DQ7. Depending on when the
Table 7.31. Unlock Bypass Program
(LLD Function = lld_UnlockBypassProgramCmd)
Cycle
Description
Operation
Byte Address
Word Address
Data
1
Program Setup Command
Write
Base + xxxh
Base +xxxh
00A0h
2
Program Command
Write
Program Address
Program Data
Table 7.32. Unlock Bypass Reset
(LLD Function = lld_UnlockBypassResetCmd)
Cycle
Description
Operation
Byte Address
Word Address
Data
1
Reset Cycle 1
Write
Base + xxxh
Base +xxxh
0090h
2
Reset Cycle 2
Write
Base + xxxh
Base +xxxh
0000h
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