參數(shù)資料
型號(hào)： S29WS128N0LBFW010
廠商： SPANSION LLC
元件分類(lèi)： PROM
英文描述： 256/128/64 MEGABIT CMOS 1.8 VOLT ONLY SIMULTANEOUS READ/WRITE BURST MODE FLASH MEMORY
中文描述： 8M X 16 FLASH 1.8V PROM, 70 ns, PBGA84
封裝： 11.60 X 8 MM, LEAD FREE, PLASTIC, FBGA-84
文件頁(yè)數(shù)： 66/95頁(yè)
文件大?。?/td> 1745K
代理商： S29WS128N0LBFW010
October 29, 2004 S29WSxxxN_00_F0
69
Pre l i m i n a r y
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven
cycles.
2. If any burst address occurs at “address + 1”, “address + 2”, or “address + 3”, additional clock delay cycles are inserted, and are indicated
by RDY.
3. The device is in synchronous mode with wrap around.
4. D8–DF in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. Starting address in figure
is the 4th address in range (0-F).
Figure 11.8. 8-word Linear Burst with Wrap Around
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven
cycles. Clock is set for active rising edge.
2. If any burst address occurs at “address + 1”, “address + 2”, or “address + 3”, additional clock delay cycles are inserted, and are indicated
by RDY.
3. The device is in asynchronous mode with out wrap around.
4. DC–D13 in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. Starting address in figure
is the 1st address in range (c-13).
Figure 11.9. 8-word Linear Burst without Wrap Around
DC
DD
OE#
Data
Addresses
Ac
AVD#
RDY
CLK
CE#
tCES
tACS
tAVC
tAVD
tACH
tOE
tIACC
tAOE
tBDH
DE
DF
DB
7 cycles for initial access shown.
Hi-Z
tRACC
12
3
4
5
6
7
tRDYS
tBACC
tCR
D8
tRACC
DC
DD
OE#
Data
Addresses
Ac
AVD#
RDY
CLK
CE#
tCES
tACS
tAVC
tAVD
tACH
tOE
tIACC
tBDH
DE
DF
D13
Hi-Z
tRACC
12
3
4
5
6
7
tRDYS
tBACC
tCR
D10
tRACC
tAOE
7 cycles for initial access shown.
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