參數(shù)資料
型號(hào)： S29WS128N0LBFW010
廠商： SPANSION LLC
元件分類： PROM
英文描述： 256/128/64 MEGABIT CMOS 1.8 VOLT ONLY SIMULTANEOUS READ/WRITE BURST MODE FLASH MEMORY
中文描述： 8M X 16 FLASH 1.8V PROM, 70 ns, PBGA84
封裝： 11.60 X 8 MM, LEAD FREE, PLASTIC, FBGA-84
文件頁(yè)數(shù)： 35/95頁(yè)
文件大小： 1745K
代理商： S29WS128N0LBFW010
40
S29WSxxxN_00_F0 October 29, 2004
Pr e l i m i n a r y
The accelerated chip program and erase functions must not be used more than 10
times per sector. In addition, accelerated chip program and erase should be performed at
room temperature (25
°C ±10°C).
If the system asserts VHH on this input, the device automatically enters the aforementioned
Unlock Bypass mode and uses the higher voltage on the input to reduce the time required for
program and erase operations. The system can then use the Write Buffer Load command se-
quence provided by the Unlock Bypass mode. Note that if a “Write-to-Buffer-Abort Reset” is
required while in Unlock Bypass mode, the full 3-cycle RESET command sequence must be
used to reset the device. Removing VHH from the ACC input, upon completion of the embed-
ded program or erase operation, returns the device to normal operation.
Sectors must be unlocked prior to raising ACC to VHH.
The ACC pin must not be at VHH for operations other than accelerated programming and
accelerated chip erase, or device damage may result.
The ACC pin must not be left floating or unconnected; inconsistent behavior of the device
may result.
tACC locks all sector if set to VIL; tACC should be set to VIH for all other conditions.
7.5.8 Unlock Bypass
The device features an Unlock Bypass mode to facilitate faster word programming. Once the
device enters the Unlock Bypass mode, only two write cycles are required to program data,
instead of the normal four cycles.
This mode dispenses with the initial two unlock cycles required in the standard program com-
mand sequence, resulting in faster total programming time. The “Command Definition
Summary” section shows the requirements for the unlock bypass command sequences.
During the unlock bypass mode, only the Read, Unlock Bypass Program and Unlock Bypass
Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-
cycle unlock bypass reset command sequence. The first cycle must contain the bank address
and the data 90h. The second cycle need only contain the data 00h. The bank then returns
to the read mode.
The following are C source code examples of using the unlock bypass entry, program, and exit
functions. Refer to the Spansion Low Level Driver User’s Guide (available soon on
www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory
software development guidelines.
/* Example: Unlock Bypass Entry Command
*/
*( (UINT16 *)bank_addr + 0x555 ) = 0x00AA;
/* write unlock cycle 1
*/
*( (UINT16 *)bank_addr + 0x2AA ) = 0x0055;
/* write unlock cycle 2
*/
*( (UINT16 *)bank_addr + 0x555 ) = 0x0020;
/* write unlock bypass command
*/
/* At this point, programming only takes two write cycles.
*/
/* Once you enter Unlock Bypass Mode, do a series of like
*/
/* operations (programming or sector erase) and then exit
*/
/* Unlock Bypass Mode before beginning a different type of
*/
/* operations.
*/
Software Functions and Sample Code
Table 7.30. Unlock Bypass Entry
(LLD Function = lld_UnlockBypassEntryCmd)
Cycle
Description
Operation
Byte Address
Word Address
Data
1
Unlock
Write
Base + AAAh
Base + 555h
00AAh
2
Unlock
Write
Base + 554h
Base + 2AAh
0055h
3
Entry Command
Write
Base + AAAh
Base + 555h
0020h
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