參數(shù)資料
型號(hào)： S29WS128N0LBFW010
廠商： SPANSION LLC
元件分類： PROM
英文描述： 256/128/64 MEGABIT CMOS 1.8 VOLT ONLY SIMULTANEOUS READ/WRITE BURST MODE FLASH MEMORY
中文描述： 8M X 16 FLASH 1.8V PROM, 70 ns, PBGA84
封裝： 11.60 X 8 MM, LEAD FREE, PLASTIC, FBGA-84
文件頁(yè)數(shù)： 42/95頁(yè)
文件大?。?/td> 1745K
代理商： S29WS128N0LBFW010
October 29, 2004 S29WSxxxN_00_F0
47
Pre l i m i n a r y
7.6 Simultaneous Read/Write
The simultaneous read/write feature allows the host system to read data from one bank of
memory while programming or erasing another bank of memory. An erase operation may also
be suspended to read from or program another location within the same bank (except the
sector being erased). Figure 11.23, Back-to-Back Read/Write Cycle Timings, shows how read
and write cycles may be initiated for simultaneous operation with zero latency. Refer to the
DC Characteristics (CMOS Compatible) table for read-while-program and read-while-erase
current specification.
7.7 Writing Commands/Command Sequences
When the device is configured for Asynchronous read, only Asynchronous write operations are
allowed, and CLK is ignored. When in the Synchronous read mode configuration, the device
is able to perform both Asynchronous and Synchronous write operations. CLK and AVD# in-
duced address latches are supported in the Synchronous programming mode. During a
synchronous write operation, to write a command or command sequence (which includes pro-
gramming data to the device and erasing sectors of memory), the system must drive AVD#
and CE# to VIL, and OE# to VIH when providing an address to the device, and drive WE# and
CE# to VIL, and OE# to VIH when writing commands or data. During an asynchronous write
operation, the system must drive CE# and WE# to VIL and OE# to VIH when providing an
address, command, and data. Addresses are latched on the last falling edge of WE# or CE#,
while data is latched on the 1st rising edge of WE# or CE#. An erase operation can erase one
sector, multiple sectors, or the entire device. Tables 6.1–6.3 indicate the address space that
each sector occupies. The device address space is divided into sixteen banks: Banks 1
through 14 contain only 64 Kword sectors, while Banks 0 and 15 contain both 16 Kword boot
sectors in addition to 64 Kword sectors. A “bank address” is the set of address bits required
to uniquely select a bank. Similarly, a “sector address” is the address bits required to uniquely
select a sector. ICC2 in “DC Characteristics” represents the active current specification for the
write mode. “AC Characteristics-Synchronous” and “AC Characteristics-Asynchronous” con-
tain timing specification tables and timing diagrams for write operations.
7.8 Handshaking
The handshaking feature allows the host system to detect when data is ready to be read by
simply monitoring the RDY (Ready) pin, which is a dedicated output and controlled by CE#.
When the device is configured to operate in synchronous mode, and OE# is low (active), the
initial word of burst data becomes available after either the falling or rising edge of the RDY
pin (depending on the setting for bit 10 in the Configuration Register). It is recommended
that the host system set CR13–CR11 in the Configuration Register to the appropriate number
of wait states to ensure optimal burst mode operation (see Table 7.15, Configuration
Bit 8 in the Configuration Register allows the host to specify whether RDY is active at the same
time that data is ready, or one cycle before data is ready.
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