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參數(shù)資料
| 型號(hào)： | S29WS128N0LBFW010 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 256/128/64 MEGABIT CMOS 1.8 VOLT ONLY SIMULTANEOUS READ/WRITE BURST MODE FLASH MEMORY |
| 中文描述： | 8M X 16 FLASH 1.8V PROM, 70 ns, PBGA84 |
| 封裝： | 11.60 X 8 MM, LEAD FREE, PLASTIC, FBGA-84 |
| 文件頁(yè)數(shù)： | 68/95頁(yè) |
| 文件大?。?/td> | 1745K |
| 代理商： | S29WS128N0LBFW010 |
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70
S29WSxxxN_00_F0 October 29, 2004
Pr e l i m i n a r y
Notes:
1. Figure assumes 6 wait states for initial access and synchronous read.
2. The Set Configuration Register command sequence has been written with CR8=0; device will output RDY one
cycle before valid data.
Figure 11.10. Linear Burst with RDY Set One Cycle Before Data
11.8.4 AC Characteristics—Asynchronous Read
Note: Not 100% tested.
Parameter
Description
54 MHz
66 MHz
80
MHz
Unit
JEDEC
Standard
tCE
Access Time from CE# Low
Max
70
ns
tACC
Asynchronous Access Time
Max
70
ns
tAVDP
AVD# Low Time
Min
8
ns
tAAVDS
Address Setup Time to Rising Edge of AVD#
Min
4
ns
tAAVDH
Address Hold Time from Rising Edge of AVD#
Min
7
6
ns
tOE
Output Enable to Output Valid
Max
13.5
11.2
ns
tOEH
Output Enable Hold Time
Read
Min
0
ns
Toggle and Data# Polling
Min
10
ns
tOEZ
Output Enable to High Z (see Note)
Max
10
ns
tCAS
CE# Setup Time to AVD#
Min
0
ns
Da+1
Da
Da+2
Da+3
Da + n
OE#
Data
Addresses
Aa
AVD#
RDY
CLK
CE#
tCES
tACS
tAVC
tAVD
tACH
tOE
tRACC
tOEZ
tCEZ
tIACC
tAOE
tBDH
6 wait cycles for initial access shown.
Hi-Z
12
3
4
5
6
tRDYS
tBACC
tCR
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