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參數(shù)資料
| 型號： | S29WS128N0LBFW010 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 256/128/64 MEGABIT CMOS 1.8 VOLT ONLY SIMULTANEOUS READ/WRITE BURST MODE FLASH MEMORY |
| 中文描述： | 8M X 16 FLASH 1.8V PROM, 70 ns, PBGA84 |
| 封裝： | 11.60 X 8 MM, LEAD FREE, PLASTIC, FBGA-84 |
| 文件頁數(shù)： | 54/95頁 |
| 文件大小： | 1745K |
| 代理商： | S29WS128N0LBFW010 |
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58
S29WSxxxN_00_F0 October 29, 2004
Pr e l i m i n a r y
9
Power Conservation Modes
9.1 Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby
mode. In this mode, current consumption is greatly reduced, and the outputs are placed in
the high impedance state, independent of the OE# input. The device enters the CMOS
standby mode when the CE# and RESET# inputs are both held at VCC ± 0.2 V. The device
requires standard access time (tCE) for read access, before it is ready to read data. If the de-
vice is deselected during erasure or programming, the device draws active current until the
operation is completed. ICC3 in “DC Characteristics” represents the standby current
specification
9.2 Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption while in asynchronous
mode. the device automatically enables this mode when addresses remain stable for tACC +
20 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals.
Standard address access timings provide new data when addresses are changed. While in
sleep mode, output data is latched and always available to the system. While in synchronous
mode, the automatic sleep mode is disabled. Note that a new burst operation is required to
provide new data. ICC6 in “DC Characteristics” represents the automatic sleep mode current
specification.
9.3 Hardware RESET# Input Operation
The RESET# input provides a hardware method of resetting the device to reading array data.
When RESET# is driven low for at least a period of tRP, the device immediately terminates any
operation in progress, tristates all outputs, resets the configuration register, and ignores all
read/write commands for the duration of the RESET# pulse. The device also resets the inter-
nal state machine to reading array data. The operation that was interrupted should be
reinitiated once the device is ready to accept another command sequence to ensure data
integrity.
When RESET# is held at VSS ± 0.2 V, the device draws CMOS standby current (ICC4). If RE-
SET# is held at VIL but not within VSS ± 0.2 V, the standby current will be greater.
RESET# may be tied to the system reset circuitry and thus, a system reset would also reset
the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.
9.4 Output Disable (OE#)
When the OE# input is at VIH, output from the device is disabled. The outputs are placed in
the high impedance state.
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