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參數(shù)資料
| 型號(hào)： | S1C60N08F0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 94/145頁(yè) |
| 文件大?。?/td> | 1118K |
| 代理商： | S1C60N08F0A0100 |
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I-40
EPSON
S1C60N08 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
SCTRG: Clock trigger (2E7HD3)
This is a trigger to start input/output of synchronous clock.
When "1" is written : Trigger
When "0" is written : No operation
Read-out : Always "0"
When this trigger is supplied to the serial interface activating circuit, the synchronous clock (SCLK)
input/output is started.
As a trigger condition, it is required that data writing or reading on data registers SD0–SD7 be performed
prior to writing "1" to SCTRG. (The internal circuit of the serial interface is initiated through data writ-
ing/reading on data registers SD0–SD7.)
Supply trigger only once every time the serial interface is placed in the RUN state. Refrain from
perfoming trigger input multiple times, as leads to malfunctioning.
Moreover, when the synchronous clock SCLK is external clock, start to input the external clock after the
trigger.
SIOF (R11): Serial interface status (2ECHD1)
Indicates the running status of the serial interface.
When "1" is read out : RUN status
When "0" is read out : STOP status
Writing : Invalid
The RUN status is indicated from immediatery after "1" is written to SCTRG bit through to the end of
serial data input/output.
4.7.6 Programming notes
(1) If the bit data of SE2 changes while SCLK is in the master mode, a hazard will be output to the SCLK
pin. If this poses a problem for the system, be sure to set the SCLK to the external clock if the bit data
of SE2 is to be changed.
(2) Be sure that read-out of the interrupt factor flag (ISIO) is done only when the serial port is in the STOP
status (SIOF = "0") and the DI status (interrupt flag = "0"). If read-out is performed while the serial
data is in the RUN status (during input or output), the data input or output will be suspended and the
initial status resumed. Read-out during the EI status (interrupt flag = "1") causes malfunctioning.
(3) When using the serial interface in the master mode, the synchronous clock uses the CPU system clock.
Accordingly, do not change the system clock (fOSC1
fOSC3) while the serial interface is operating.
(4) Perform data writing/reading to data registers SD0–SD7 only while the serial interface is halted (i.e.,
the synchronous clock is neither being input or output).
(5) As a trigger condition, it is required that data writing or reading on data registers SD0–SD7 be per-
formed prior to writing "1" to SCTRG. (The internal circuit of the serial interface is initiated through
data writing/reading on data registers SD0–SD7.) Supply trigger only once every time the serial
interface is placed in the RUN state. Moreover, when the synchronous clock SCLK is external clock,
start to input the external clock after the trigger.
(6) Be sure that writing to the interrupt mask register is done only in the DI status (interrupt flag = "0").
Writing to the interrupt mask register while in the EI status (interrupt flag = "1") may cause malfunc-
tion.
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