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參數(shù)資料
| 型號： | S1C60N08F0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 126/145頁 |
| 文件大?。?/td> | 1118K |
| 代理商： | S1C60N08F0A0100 |
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S1C60N08 TECHNICAL HARDWARE
EPSON
I-69
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (BLD Circuit)
4.14.3 Detection timing of BLD circuit
This section explains the timing for when the BLD circuit writes the result of the source voltage detection
to the BLD latch.
Turning the BLD operation ON/OFF is controlled through the software (HLMOD, BLS). Moreover, when
a drop in source voltage (BLD0 = "1") is detected by the sub-BLD circuit, BLD operation is periodically
performed by the hardware until the source voltage is recovered (BLD0 = "0").
The result of the source voltage detection is written to the BLD latch by the BLD circuit, and this data can
be read out by the software to find the status of the source voltage.
There are three status, explained below, for the detection timing of the BLD circuit.
(1) Sampling with HLMOD set to "1"
When HLMOD is set to "1" and BLD sampling executed, the detection results can be written to the
BLD latch in the following two timings.
Immediately after the time for one instruction cycle has ended immediately after HLMOD = "1"
Immediately after sampling in the 2 Hz cycle output by the clock timer while HLMOD = "1"
Consequently, the BLD latch data is loaded immediately after HLMOD has been set to "1", and at the
same time the new detection result is written in 2 Hz cycles.
To obtain a stable BLD detection result, the BLD circuit must be set to ON with at least 100 sec.
When the CPU system clock is fOSC3 in the S1C60A08, the detection result at the timing in above
may be invalid or incorrect. (When performing BLD detection using the timing in , be sure that the
CPU system clock is fOSC1.)
(2) Sampling with BLS set to "1"
When BLS is set to "1", BLD detection is executed. As soon as BLS is reset to "0" the detection result is
loaded to the BLD latch. To obtain a stable BLD detection result, the BLD circuit must be set to ON
with at least 100 sec. Hence, to obtain the BLD detection result, follow the programming sequence
below.
0. Set HLMOD to "1"
(only when the CPU system clock is fOSC3 in the S1C60A08)
1. Set BLS to "1"
2. Maintain at 100 sec minimum
3. Set BLS to "0"
4. Read out BLD
5. Set HLMOD to "0"
(only when the CPU system clock is fOSC3 in the S1C60A08)
However, when a crystal oscillation clock (fOSC1) is selected for the CPU system clock in the
S1C60N08, S1C60L08, and S1C60A08, the instruction cycles are long enough, so that there is no need
for concern about maintaining 100 sec for the BLS = "1" with the software.
(3) Sampling by hardware when sub-BLD latch is set to "1"
When BLD0 (sub-BLD latch) is set to "1", the detection results can be written to the BLD0 (sub-BLD
latch) and BLD1 (BLD latch) in the following two timings (same as that sampling with HLMOD set to
"1").
Immediately after the time for one instruction cycle has ended immediately after BLD0 = "1"
Immediately after sampling in the 2 Hz cycle output by the clock timer while BLD0 = "1"
Consequently, the BLD0 (sub-BLD latch) and BLD1 (BLD latch) data are loaded immediately after
BLD0 (sub-BLD latch) has been set to "1", and at the same time the new detection result is written in 2
Hz cycles.
To obtain a stable BLD detection result, the BLD circuit must be set to ON with at least 100 sec.
When the CPU system clock is fOSC3 in the S1C60A08, the detection result at the timing in above
may be invalid or incorrect.
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