參數(shù)資料
型號： S1C60N08F0A0100
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, PQFP100
封裝： PLASTIC, QFP-100
文件頁數(shù)： 10/145頁
文件大?。?/td> 1118K
代理商： S1C60N08F0A0100
S1C60N08 TECHNICAL HARDWARE
EPSON
I-95
CHAPTER 7: ELECTRICAL CHARACTERISTICS
7.4 Analog Circuit Characteristics and Current Consumption
S1C60N08 (Normal operating mode)
Item
LCD drive voltage
BLD voltage 1
BLD circuit response time
Sub-BLD voltage
Sub-BLD circuit response time
Analog comparator
input voltage
Analog comparator
offset voltage
Analog comparator
response time
Current consumption
1
2
Unless otherwise specified:
VDD=0V, VSS=-3.0V, fOSC1=32.768kHz, Ta=25
°C, CG=25pF, VS1/VL1–VL3 are internal voltage, C1–C5=0.1F
Symbol
VL1
VL2
VL3
VB0
VB1
VB2
VB3
VB4
VB5
VB6
VB7
tB
VBS
tBS
VIP
VIM
VOF
tAMP
IOP
Unit
V
sec
V
sec
V
mV
msec
A
Max.
1/2VL2
×0.9
-1.90
3/2VL2
×0.9
-2.05
-2.10
-2.15
-2.20
-2.25
-2.30
-2.35
-2.40
100
-2.25
100
VDD-0.9
10
3
2.0
4.0
Typ.
-2.10
-2.20
-2.25
-2.30
-2.35
-2.40
-2.45
-2.50
-2.55
-2.40
1.0
2.2
Min.
1/2VL2
- 0.1
-2.30
3/2VL2
- 0.1
-2.35
-2.40
-2.45
-2.50
-2.55
-2.60
-2.65
-2.70
-2.55
VSS+0.3
The relationships among VB0–VB7 are VB0>VB1>VB2>...VB5>VB6>VB7.
The BLD circuit, sub-BLD circuit and analog comparator are in the OFF status.
Condition
Connect 1 M
load resistor between VDD and VL1
(without panel load)
Connect 1 M
load resistor between VDD and VL2
(without panel load)
Connect 1 M
load resistor between VDD and VL3
(without panel load)
BLC="0"
BLC="1"
BLC="2"
BLC="3"
BLC="4"
BLC="5"
BLC="6"
BLC="7"
Non-inverted input (AMPP)
Inverted input (AMPM)
VIP=-1.5V
VIM=VIP
±15mV
During HALT
Without
During operation 2
panel load
S1C60N08 (Heavy load protection mode)
Item
LCD drive voltage
BLD voltage 1
BLD circuit response time
Sub-BLD voltage
Sub-BLD circuit response time
Analog comparator
input voltage
Analog comparator
offset voltage
Analog comparator
response time
Current consumption
1
2
Unless otherwise specified:
VDD=0V, VSS=-3.0V, fOSC1=32.768kHz, Ta=25
°C, CG=25pF, VS1/VL1–VL3 are internal voltage, C1–C5=0.1F
Symbol
VL1
VL2
VL3
VB0
VB1
VB2
VB3
VB4
VB5
VB6
VB7
tB
VBS
tBS
VIP
VIM
VOF
tAMP
IOP
Unit
V
sec
V
sec
V
mV
msec
A
Max.
1/2VL2
×0.9
-1.90
3/2VL2
×0.9
-2.05
-2.10
-2.15
-2.20
-2.25
-2.30
-2.35
-2.40
100
-2.25
100
VDD-0.9
10
3
20
25
Typ.
-2.10
-2.20
-2.25
-2.30
-2.35
-2.40
-2.45
-2.50
-2.55
-2.40
10
12
Min.
1/2VL2
- 0.1
-2.30
3/2VL2
- 0.1
-2.35
-2.40
-2.45
-2.50
-2.55
-2.60
-2.65
-2.70
-2.55
VSS+0.3
The relationships among VB0–VB7 are VB0>VB1>VB2>...VB5>VB6>VB7.
The BLD circuit and sub-BLD circuit are in the ON status (HLMOD="1", BLS="0").
The analog comparator is in the OFF status.
Condition
Connect 1 M
load resistor between VDD and VL1
(without panel load)
Connect 1 M
load resistor between VDD and VL2
(without panel load)
Connect 1 M
load resistor between VDD and VL3
(without panel load)
BLC="0"
BLC="1"
BLC="2"
BLC="3"
BLC="4"
BLC="5"
BLC="6"
BLC="7"
Non-inverted input (AMPP)
Inverted input (AMPM)
VIP=-1.5V
VIM=VIP
±15mV
During HALT
Without
During operation 2
panel load
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