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參數(shù)資料
| 型號： | S1C60N08F0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 74/145頁 |
| 文件大?。?/td> | 1118K |
| 代理商： | S1C60N08F0A0100 |
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I-22
EPSON
S1C60N08 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
The input interrupt timing for K00–K03 and K10 depends on the value set for the input comparison
registers (KCP00–KCP03 and KCP10). Interrupt can be selected to occur at the rising or falling edge of the
input.
The interrupt mask registers (EIK00–EIK03, EIK10) enables the interrupt mask to be selected individually
for K00–K03 and K10. However, whereas the interrupt function is enabled inside K00–K03, the interrupt
occurs when the contents change from matching those of the input comparison register to non-matching
contents. Interrupt for K10 can be generated by setting the same conditions individually.
When the interrupt is generated, the interrupt factor flag (IK0 and IK1) is set to "1".
Figure 4.4.2.2 shows an example of an interrupt for K00–K03.
Interrupt mask register
EIK03
1
EIK02
1
EIK01
1
EIK00
0
Input port
(1)
(Initial value)
Interrupt generation
K03
1
K02
0
K01
1
K00
0
Input comparison register
KCP03
1
KCP02
0
KCP01
1
KCP00
0
With the above setting, the interrupt of K00–K03 is generated under the following condition:
(2)
K03
1
K02
0
K01
1
K00
1
(3)
K03
0
K02
0
K01
1
K00
1
(4)
K03
0
K02
1
K01
1
K00
1
Because K00 interrupt is masked, interrupt will be
generated when no matching occurs between the
contents of the 3 bits K01–K03 and the 3 bits input
comparison register KCP01–KCP03.
Fig. 4.4.2.2 Example of interrupt of K00–K03
K00 is masked by the interrupt mask register (EIK00), so that an interrupt does not occur at (2). At (3),
K03 changes to "0"; the data of the terminal that is interrupt enabled no longer matches the data of the
input comparison register, so that interrupt occurs. As already explained, the condition for the interrupt
to occur is the change in the port data and contents of the input comparison register from matching to
nonmatching. Hence, in (4), when the nonmatching status changes to another nonmatching status, an
interrupt does not occur. Further, terminals that have been masked for interrupt do not affect the condi-
tions for interrupt generation.
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