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| 型號(hào)： | S1C60N08F0A0100 |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 88/145頁(yè) |
| 文件大?。?/td> | 1118K |
| 代理商： | S1C60N08F0A0100 |
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S1C60N08 TECHNICAL HARDWARE
EPSON
I-35
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
Note: When using the serial interface in the master mode, CPU system clock is used as the synchronous
clock. Accordingly, when the serial interface is operating, system clock switching (fOSC1
fOSC3)
should not be performed.
A sample basic serial input/output portion connection is shown in Figure 4.7.2.1.
S1C60N08
Master mode
Slave mode
SCLK
SOUT
SIN
Input terminal
External
serial device
CLK
SOUT
SIN
READY
S1C60N08
SCLK
SOUT
SIN
R11(SIOF)
External
serial device
CLK
SOUT
SIN
Input terminal
Fig. 4.7.2.1 Sample basic connection
4.7.3 Data input/output and interrupt function
The serial interface can input/output data via the internal 8 bits shift register. The shift register operates
by synchronizing with either the synchronous clock output from SCLK terminal (master mode), or the
synchronous clock input to SCLK (slave mode).
The serial interface generates interrupt on completion of the 8 bits serial data input/output. Detection of
serial data input/output is done by the counting of the synchronous clock (SCLK); the clock completes
input/output operation when 8 counts (equivalent to 8 cycles) have been made and then generates
interrupt.
The serial data input/output procedure data is explained below:
(1) Serial data output procedure and interrupt
The serial interface is capable of outputting parallel data as serial data, in units of 8 bits.
By setting the parallel data to 4 bits registers SD0–SD3 (address 2F0H) and SD4–SD7 (address 2F1H)
individually and writing "1" to SCTRG bit (address 2E7HD3), it synchronizes with the synchronous
clock and serial data is output at the SOUT terminal. The synchronous clock used here is as follows: in
the master mode, internal clock which is output to the SCLK terminal while in the slave mode,
external clock which is input from the SCLK terminal. The serial output of the SOUT termina changes
with the rising edge of the clock that is input or output from the SCLK terminal.
The serial data to the built-in shift register is shifted with the rising edge of the SCLK signal when SE2
bit (address 2F2HD1) is "1" and is shifted with the falling edge of the SCLK signal when SE2 bit
(address 2F2HD1) is "0".
When the output of the 8 bits data from SD0 to SD7 is completed, the interrupt factor flag ISIO
(address 2F3HD0) is set to "1" and interrupt is generated. Moreover, the interrupt can be masked by
the interrupt mask register EISIO (address 2F2HD0).
(2) Serial data input procedure and interrupt
The serial interface is capable of inputting serial data as parallel data, in units of 8 bits.
The serial data is input from the SIN terminal, synchronizes with the synchronous clock, and is
sequentially read in the 8 bits shift register. As in the above item (1), the synchronous clock used here
is as follows: in the master mode, internal clock which is output to the SCLK terminal while in the
slave mode, external clock which is input from the SCLK terminal.
The serial data to the built-in shift register is read with the rising edge of the SCLK signal when SE2
bit is "1" and is read with the falling edge of the SCLK signal when SE2 bit is "0". Moreover, the shift
register is sequentially shifted as the data is fetched.
When the input of the 8 bits data from SD0 to SD7 is completed, the interrupt factor flag ISIO is set to
"1" and interrupt is generated. Moreover, the interrupt can be masked by the interrupt mask register
EISIO. Note, however, that regardless of the setting of the interrupt mask register, the interrupt factor
flag is set to "1" after input of the 8 bits data.
The data input in the shift register can be read from data registers SD0–SD7 by software.
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