參數(shù)資料
型號: S1C60N08F0A0100
元件分類: 微控制器/微處理器
英文描述: MICROCONTROLLER, PQFP100
封裝: PLASTIC, QFP-100
文件頁數(shù): 138/145頁
文件大小: 1118K
代理商: S1C60N08F0A0100
I-80
EPSON
S1C60N08 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
4.16.3 Interrupt vectors
When an interrupt request is input to the CPU, the CPU begins interrupt processing. After the program
being executed is terminated, the interrupt processing is executed in the following order.
The address data (value of program counter) of the program to be executed next is saved in the stack
area (RAM).
The interrupt request causes the value of the interrupt vector (page 1, 01H–0FH) to be set in the
program counter.
The program at the specified address is executed (execution of interrupt processing routine by
software).
Table 4.16.3.1 shows the correspondence of interrupt requests and interrupt vectors.
Note: The processing in and above take 12 cycles of the CPU system clock.
Table 4.16.3.1 Interrupt request and interrupt vectors
PC
PCS3
PCS2
PCS1
PCS0
Value
1
0
1
0
1
0
1
0
Interrupt request
Stopwatch timer interrupt
Enabled
Masked
Clock timer interrupt
Enabled
Masked
Input port interrupt
Enabled
Masked
Serial interface interrupt
Enabled
Masked
The four low-order bits of the program counter are indirectly addressed through the interrupt request.
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