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| 型號(hào)： | S1C60N08F0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 85/145頁(yè) |
| 文件大小： | 1118K |
| 代理商： | S1C60N08F0A0100 |
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I-32
EPSON
S1C60N08 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)
4.6.4 Control of I/O ports
Table 4.6.4.1 lists the I/O ports' control bits and their addresses.
Table 4.6.4.1 I/O port control bits
Address
Comment
D3
D2
Register
D1
D0
Name
Init 1
10
2EEH
TMRST SWRUN SWRST
IOC0
WR/W
TMRST3
SWRUN
SWRST3
IOC0
Reset
0
Reset
0
Reset
Run
Reset
Output
–
Stop
–
Input
Clock timer reset
Stopwatch timer Run/Stop
Stopwatch timer reset
I/O control register 0 (P00–P03)
2EDH
P03
P02
P01
P00
R/W
P03
P02
P01
P00
– 2
High
Low
I/O port data (P00–P03)
Output latch is reset at initial reset
5 Undefined
1
2
Initial value at initial reset
Not set in the circuit
3
4
Always "0" being read
Reset (0) immediately after being read
2FEH
PRSM CLKCHG OSCC
IOC1
R/W
PRSM
CLKCHG
OSCC
IOC1
0
38 kHz
OSC3
On
Output
32 kHz
OSC1
Off
Input
OSC1 prescaler selection
CPU clock switch
OSC3 oscillation On/Off
I/O control register (P10–P13)
2FDH
P13
P12
P11
P10
R/W
P13
P12
P11
P10
– 2
High
Low
I/O port data (P10–P13)
Output latch is reset at initial reset
P00–P03, P10–P13: I/O port data (2EDH, 2FDH)
I/O port data can be read and output data can be set through these ports.
When writing data
When "1" is written : High level
When "0" is written : Low level
When an I/O port is set to the output mode, the written data is output unchanged from the I/O port
terminal. When "1" is written as the port data, the port terminal goes high (VDD), and when "0" is written,
the level goes low (VSS).
Port data can be written also in the input mode.
When reading data out
When "1" is read out : High level
When "0" is read out : Low level
The terminal voltage level of the I/O port is read out. When the I/O port is in the input mode the voltage
level being input to the port terminal can be read out; in the output mode the output voltage level can be
read. When the terminal voltage is high (VDD) the port data that can be read is "1", and when the terminal
voltage is low (VSS) the data is "0".
Further, the built-in pull-down resistance goes ON during read-out, so that the I/O port terminal is
pulled down.
Notes: When the I/O port is set to the output mode and a low-impedance load is connected to the port
terminal, the data written to the register may differ from the data read out.
When the I/O port is set to the input mode and a low-level voltage (VSS) is input, erroneous input
results if the time constant of the capacitive load of the input line and the built-in pull-down
resistance load is greater than the read-out time. When the input data is being read out, the time
that the input line is pulled down is equivalent to 1.5 cycles of the CPU system clock. However,
the electric potential of the terminals must be settled within 0.5 cycles. If this condition cannot be
fulfilled, some measure must be devised such as arranging pull-down resistance externally, or
performing multiple read-outs.
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