- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98068 > S1C60N08F0A0100 MICROCONTROLLER, PQFP100 PDF資料下載
參數(shù)資料
| 型號(hào)： | S1C60N08F0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 78/145頁(yè) |
| 文件大?。?/td> | 1118K |
| 代理商： | S1C60N08F0A0100 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)當(dāng)前第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)
I-26
EPSON
S1C60N08 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
4.4.5 Programming notes
(1) When input ports are changed from high to low by pull-down resistance, the fall of the waveform is
delayed on account of the time constant of the pull-down resistance and input gate capacitance.
Hence, when fetching input ports, set an appropriate wait time.
Particular care needs to be taken of the key scan during key matrix configuration. Aim for a wait time
of about 1 msec.
(2) When "Use" is selected with the noise rejector mask option, a maximum delay of 1 msec occurs from
time the interrupt conditions are established until the interrupt factor flag (IK) is set to "1" (until the
interrupt is actually generated). Hence, pay attention to the timing when reading out (resetting) the
interrupt factor flag. For example, when performing a key scan with the key matrix, the key scan
changes the input status to set the interrupt factor flag, so it has to be read out to reset it. However, if
the interrupt factor flag is read out immediately after key scanning, the delay will cause the flag to be
set after read-out, so that it will not be reset.
(3) Input interrupt programing related precautions
Port K input
Factor flag set Not set
Factor flag set
Input comparison
register
Mask register
Active status
Rising edge interrupt
Falling edge interrupt
When the content of the mask register is rewritten while the port K input is in the active status, the
input interrupt factor flags are set at and , being the interrupt due to the falling edge and
the interrupt due to the rising edge.
Fig. 4.4.5.1 Input interrupt timing
When using an input interrupt, if you rewrite the content of the mask register, when the value of the
input terminal which becomes the interrupt input is in the active status, the factor flag for input
interrupt may be set.
Therefore, when using the input interrupt, the active status of the input terminal implies
input terminal = low status, when the falling edge interrupt is effected and
input terminal = high status, when the rising edge interrupt is effected.
When an interrupt is triggered at the falling edge of an input terminal, a factor flag is set with the
timing of shown in Figure 4.4.5.1. However, when clearing the content of the mask register with the
input terminal kept in the low status and then setting it, the factor flag of the input interrupt is again
set at the timing that has been set.
Consequently, when the input terminal is in the active status (low status), do not rewrite the mask
register (clearing, then setting the mask register), so that a factor flag will only set at the falling edge
in this case. When clearing, then setting the mask register, set the mask register, when the input
terminal is not in the active status (high status).
When an interrupt is triggered at the rising edge of the input terminal, a factor flag will be set at the
timing of shown in Figure 4.4.5.1. In this case, when the mask registers cleared, then set, you should
set the mask register, when the input terminal is in the low status.
In addition, when the mask register = "1" and the content of the input comparison register is rewritten
in the input terminal active status, an input interrupt factor flag may be set. Thus, you should rewrite
the content of the input comparison register in the mask register = "0" status.
(4) Read out the interrupt factor flag (IK) only in the DI status (interrupt flag = "0"). Read-out during EI
status (interrupt flag = "1") will cause malfunction.
(5) Write the interrupt mask register (EIK) only in the DI status (interrupt flag = "0"). Writing during EI
status (interrupt flag = "1") will cause malfunction.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S1C621C0D | 4-BIT, MROM, 1.3 MHz, MICROCONTROLLER, UUC74 |
| S1C62480D | 4-BIT, MROM, 2.3 MHz, MICROCONTROLLER, UUC135 |
| S1C62440F | 4-BIT, MROM, 2.3 MHz, MICROCONTROLLER, PQFP128 |
| S1C62740D | 4-BIT, MROM, 1.3 MHz, MICROCONTROLLER, UUC109 |
| S1C62920D | 4-BIT, MROM, 1.3 MHz, MICROCONTROLLER, UUC63 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S1C60N16 | 制造商:EPSON 制造商全稱:EPSON 功能描述:4-bit Single Chip Microcomputer |
| S1C60R08 | 制造商:EPSON 制造商全稱:EPSON 功能描述:4-bit Single Chip Microcomputer |
| S1C63004 | 制造商:EPSON 制造商全稱:EPSON 功能描述:CMOS 4-bit Single Chip Microcontroller |
| S1C63008 | 制造商:EPSON 制造商全稱:EPSON 功能描述:CMOS 4-bit Single Chip Microcontroller |
| S1C63016 | 制造商:EPSON 制造商全稱:EPSON 功能描述:CMOS 4-bit Single Chip Microcontroller |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。