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參數(shù)資料
| 型號： | S1C60N08F0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 144/145頁 |
| 文件大?。?/td> | 1118K |
| 代理商： | S1C60N08F0A0100 |
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I-86
EPSON
S1C60N08 TECHNICAL HARDWARE
CHAPTER 5: SUMMARY OF NOTES
LCD driver
(1) When Page 0 is selected for the display memory, the memory data and the display will not match
until the area is initialized (through, for instance, memory clear processing by the CPU). Initialize the
display memory by executing initial processing.
(2) When Page 2 is selected for the display memory, that area becomes write-only. Consequently, data
cannot be rewritten by arithmetic operations (such as AND, OR, ADD, SUB).
Clock timer
(1) The prescaler mode must be set correctly to suit the crystal oscillator to be used.
(2) When the clock timer has been reset, the interrupt factor flag (TI) may sometimes be set to "1". Conse-
quently, perform flag read-out (reset the flag) as necessary at reset.
(3) The input clock of the watchdog timer is the 2 Hz signal of the clock timer, so that the watchdog timer
may be counted up at timer reset.
Stopwatch timer
(1) The prescaler mode must be set correctly so that the stopwatch timer suits the crystal oscillator to be
used.
(2) If timer data is read out in the RUN status, the timer must be made into the STOP status, and after
data is read out the RUN status can be restored. If data is read out when a carry occurs, the data
cannot be read correctly.
Also, the processing above must be performed within the STOP interval of 976 sec (256 Hz 1/4
cycle).
Sound generator
A hazard may be observed in the output waveform of the BZ and BZ signals when data of the output
registers (R10, R13) and the buzzer frequency selection registers (BZFQ0–BZFQ2) changes.
Event counter
(1) After the event counter has written data to the EVRUN register, it operates or stops in synchroniza-
tion with the falling edge of the noise rejector clock or stops. Hence, attention must be paid to the
above timing when input signals (input to K02 and K03) are being received.
(2) To prevent erroneous reading of the event counter data, read out the counter data several times,
compare it, and use the matching data as the result.
Analog comparator
(1) To reduce current consumption, set the analog comparator to OFF when it is not necessary.
(2) After setting AMPON to "1", wait at least 3 msec for the operation of the analog comparator to
stabilize before reading the output data of the analog comparator from AMPDT.
Battery life detection (BLD) circuit
(1) It takes 100 sec from the time the BLD circuit goes ON until a stable result is obtained. For this
reason, keep the following software notes in mind:
When the CPU system clock is fOSC1
1. When detection is done at HLMOD
After writing "1" on HLMOD, read the BLD after 1 instruction has passed.
2. When detection is done at BLS
After writing "1" on BLS, write "0" after at least 100 sec has lapsed (possible with the next instruc-
tion) and then read the BLD.
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