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參數(shù)資料
| 型號： | S1C60N08F0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 127/145頁 |
| 文件大小： | 1118K |
| 代理商： | S1C60N08F0A0100 |
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I-70
EPSON
S1C60N08 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (BLD Circuit)
4.14.4 Control of BLD circuit
Table 4.14.4.1 shows the BLD circuit's control bits and their addresses.
Table 4.14.4.1 Control bits of BLD circuit
Address
Comment
D3
D2
Register
D1
D0
Name
Init 1
10
2E6H
HLMOD
BLD0 EISWIT1 EISWIT0
R/W
R
R/W
HLMOD
BLD0
EISWIT1
EISWIT0
0
Heavy load
Low
Enable
Normal
Mask
Heavy load protection mode register
Sub-BLD evaluation data
Interrupt mask register (stopwatch 1 Hz)
Interrupt mask register (stopwatch 10 Hz)
1
2
Initial value at initial reset
Not set in the circuit
3
4
Always "0" being read
Reset (0) immediately after being read
5 Undefined
2FFH
BLS
BLD1
BLC2
BLC1
BLC0
W
R
R/W
BLS
BLD1
BLC2
BLC1
BLC0
0
× 5
On
Low
Off
Normal
BLD On/Off
BLD evaluation data
Evaluation voltage setting register
0
2.20
1.05
1
2.25
1.10
2
2.30
1.15
3
2.35
1.20
4
2.40
1.25
5
2.45
1.30
6
2.50
1.35
7
2.55
1.40
(V)
[BLC2–0]
S1C60N08/60A08
S1C60L08
HLMOD: Heavy load protection mode (2E6HD3)
Sets the IC in heavy load protection mode.
When "1" is written : Heavy load protection mode is set
When "0" is written : Heavy load protection mode is released
Read-out : Valid
When HLMOD is set to "1", the IC operating status enters the heavy load protection mode and at the
same time the battery life detection of the BLD circuit is controlled (ON/OFF).
For details about the heavy load protection mode, see Section 4.15, "Heavy Load Protection Function and
Sub-BLD Circuit".
When HLMOD is set to "1", sampling control is executed for the BLD circuit ON time. There are two
types of sampling time, as follows:
(1) The time of one instruction cycle immediately after HLMOD = "1"
(2) Sampling at cycles of 2 Hz output by the clock timer while HLMOD = "1"
The BLD circuit must be made ON with at least 100 sec for the BLD circuit to respond. Hence, when the
CPU system clock is fOSC3 in the S1C60A08, the detection result at the timing in (1) above may be invalid
or incorrect. When performing BLD detection using the timing in (1), be sure that the CPU system clock is
fOSC1.
When BLD sampling is done with HLMOD set to "1", the results are written to the BLD latch in the
timing as follows:
(1) As soon as the time has elapsed for one instruction cycle immediately following HLMOD = "1"
(2) Immediately on completion of sampling at cycles of 2 Hz output by the clock timer while HLMOD = "1"
Consequently, the BLD latch data is written immediately after HLMOD is set to "1", and at the same time
the new detection result is written in 2 Hz cycles.
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