參數資料
型號: S1C60N08F0A0100
元件分類: 微控制器/微處理器
英文描述: MICROCONTROLLER, PQFP100
封裝: PLASTIC, QFP-100
文件頁數: 132/145頁
文件大小: 1118K
代理商: S1C60N08F0A0100
S1C60N08 TECHNICAL HARDWARE
EPSON
I-75
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Heavy Load Protection Function and Sub-BLD Circuit)
BLS/BLD1: BLD detection/BLD data (2FFHD3)
Controls the BLD operation.
When "0" is written : BLD detection OFF
When "1" is written : BLD detection ON
When "0" is read out : Source voltage (VDD–VSS) is higher than BLD set value
When "1" is read out : Source voltage (VDD–VSS) is lower than BLD set value
Note that the function of this bit when written is different to when read out.
When this bit is written to, ON/OFF of the BLD detection operation is controlled; when this bit is read
out, the result of the BLD detection (contents of BLD latch) is obtained. Appreciable current is consumed
during operation of BLD detection, so keep BLD detection OFF except when necessary.
When BLS is set to "1", BLD detection is executed. As soon as BLS is reset to "0" the detection result is
loaded to the BLD latch. To obtain a stable BLD detection result, the BLD circuit must be set to ON with at
least 100 sec. Hence, to obtain the BLD detection result, follow the programming sequence below.
0. Set HLMOD to "1"
(only when the CPU system clock is fOSC3 in the S1C60A08)
1. Set BLS to "1"
2. Maintain at 100 sec minimum
3. Set BLS to "0"
4. Read out BLD
5. Set HLMOD to "0"
(only when the CPU system clock is fOSC3 in the S1C60A08)
However, when a crystal oscillation clock (fOSC1) is selected for the CPU system clock in the S1C60N08,
S1C60L08, and S1C60A08, the instruction cycles are long enough, so that there is no need for concern
about maintaining 100 sec for the BLS = "1" with the software.
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