參數(shù)資料
型號: S1C60N08F0A0100
元件分類: 微控制器/微處理器
英文描述: MICROCONTROLLER, PQFP100
封裝: PLASTIC, QFP-100
文件頁數(shù): 62/145頁
文件大?。?/td> 1118K
代理商: S1C60N08F0A0100
S1C60N08 TECHNICAL HARDWARE
EPSON
I-11
CHAPTER 3: CPU, ROM, RAM
CHAPTER
3 CPU, ROM, RAM
3.1 CPU
The S1C60N08 Series employs the core CPU S1C6200C for the CPU, so that register configuration,
instructions and so forth are virtually identical to those in other family processors using the S1C6200/
6200A/6200B/6200C.
Refer to the "S1C6200/6200A Core CPU Manual" for details about the core CPU.
Note the following points with regard to the S1C60N08 Series:
(1) The SLEEP operation is not assumed, so the SLP instruction cannot be used.
(2) Because the ROM capacity is 4,096 words, bank bits are unnecessary and PCB and NBP are not used.
(3) RAM is set up to four pages, so only the two low-order bits are valid for the page portion (XP, YP) of
the index register that specifies addresses. (The two high-order bits are ignored.)
3.2 ROM
The built-in ROM, a mask ROM for loading the program, has a capacity of 4,096 steps, 12 bits each. The
program area is 16 pages (0–15), each of 256 steps (00H–FFH). After initial reset, the program start
address is page 1, step 00H. The interrupt vector is allocated to page 1, steps 01H–0FH.
Step 00H
Step 01H
Step 0FH
Step 10H
Step FFH
12 bits
Program start address
Interrupt vector area
Bank 0
Program area
Page 0
Page 1
Page 2
Page 3
Page 15
Fig. 3.2.1 ROM configuration
3.3 RAM
The RAM, a data memory for storing a variety of data, has a capacity of 832 words, 4-bit words. When
programming, keep the following points in mind:
(1) Part of the data memory is used as stack area when saving subroutine return addresses and registers,
so be careful not to overlap the data area and stack area.
(2) Subroutine calls and interrupts take up three words on the stack.
(3) Data memory 000H–00FH is the memory area pointed by the register pointer (RP).
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