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參數(shù)資料
| 型號(hào)： | S1C60N08F0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 128/145頁(yè) |
| 文件大?。?/td> | 1118K |
| 代理商： | S1C60N08F0A0100 |
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S1C60N08 TECHNICAL HARDWARE
EPSON
I-71
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (BLD Circuit)
BLS/BLD1: BLD detection/BLD data (2FFHD3)
Controls the BLD operation.
When "0" is written : BLD detection OFF
When "1" is written : BLD detection ON
When "0" is read out : Source voltage (VDD–VSS) is higher than BLD set value
When "1" is read out : Source voltage (VDD–VSS) is lower than BLD set value
Note that the function of this bit when written is different to when read out.
When this bit is written to, ON/OFF of the BLD detection operation is controlled; when this bit is read
out, the result of the BLD detection (contents of BLD latch) is obtained. Appreciable current is consumed
during operation of BLD detection, so keep BLD detection OFF except when necessary.
When BLS is set to "1", BLD detection is executed. As soon as BLS is reset to "0" the detection result is
loaded to the BLD latch. To obtain a stable BLD detection result, the BLD circuit must be set to ON with at
least 100 sec. Hence, to obtain the BLD detection result, follow the programming sequence below.
0. Set HLMOD to "1"
(only when the CPU system clock is fOSC3 in the S1C60A08)
1. Set BLS to "1"
2. Maintain at 100 sec minimum
3. Set BLS to "0"
4. Read out BLD
5. Set HLMOD to "0"
(only when the CPU system clock is fOSC3 in the S1C60A08)
However, when a crystal oscillation clock (fOSC1) is selected for the CPU system clock in the S1C60N08,
S1C60L08, and S1C60A08, the instruction cycles are long enough, so that there is no need for concern
about maintaining 100 sec for the BLS = "1" with the software.
4.14.5 Programming notes
(1) It takes 100 sec from the time the BLD circuit goes ON until a stable result is obtained. For this
reason, keep the following software notes in mind:
When the CPU system clock is fOSC1
1. When detection is done at HLMOD
After writing "1" on HLMOD, read the BLD after 1 instruction has passed.
2. When detection is done at BLS
After writing "1" on BLS, write "0" after at least 100 sec has lapsed (possible with the next instruc-
tion) and then read the BLD.
When the CPU system clock is fOSC3 (in case of S1C60A08 only)
1. When detection is done at HLMOD
After writing "1" on HLMOD, read the BLD after 0.6 second has passed. (HLMOD holds "1" for at
least 0.6 second)
2. When detection is done at BLS
Before writing "1" on BLS, write "1" on HLMOD first; after at least 100 sec has lapsed after
writing "1" on BLS, write "0" on BLS and then read the BLD.
(2) BLS resides in the same bit at the same address as BLD1, and one or the other is selected by write or
read operation. This means that arithmetic operations (AND, OR, ADD, SUB and so forth) cannot be
used for BLS control.
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相關(guān)代理商/技術(shù)參數(shù) |
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| S1C63016 | 制造商:EPSON 制造商全稱:EPSON 功能描述:CMOS 4-bit Single Chip Microcontroller |
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