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參數(shù)資料
| 型號： | S1C60N08F0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 120/145頁 |
| 文件大?。?/td> | 1118K |
| 代理商： | S1C60N08F0A0100 |
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I-64
EPSON
S1C60N08 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Event Counter)
4.12.4 Control of event counter
Table 4.12.4.1 shows the event counter control bits and their addresses.
Table 4.12.4.1 Control bits of event counter
Address
Comment
D3
D2
Register
D1
D0
Name
Init 1
10
5 Undefined
1
2
Initial value at initial reset
Not set in the circuit
3
4
Always "0" being read
Reset (0) immediately after being read
2F8H
EV03
EV02
EV01
EV00
R
EV03
EV02
EV01
EV00
0
Event counter 0 (low-order 4 bits)
2F9H
EV07
EV06
EV05
EV04
R
EV07
EV06
EV05
EV04
0
Event counter 0 (high-order 4 bits)
2FAH
EV13
EV12
EV11
EV10
R
EV13
EV12
EV11
EV10
0
Event counter 1 (low-order 4 bits)
2FCH
EVSEL ENRUN EV1RST EV0RST
R/W
W
EVSEL
EVRUN
EV1RST3
EV0RST3
0
Reset
Separate
Run
Reset
Phase
Stop
–
Event counter mode selection
Event counter Run/Stop
Event counter 1 reset
Event counter 0 reset
2FBH
EV17
EV16
EV15
EV14
R
EV17
EV16
EV15
EV14
0
Event counter 1 (high-order 4 bits)
EV00–EV03: Event counter 0 low-order data (2F8H)
The four low-order data bits of event counter 0 are read out.
These four bits are read-only, and cannot be used for writing.
At initial reset, event counter 0 is set to "00H".
EV04–EV07: Event counter 0 high-order data (2F9H)
The four high-order data bits of event counter 0 are read out.
These four bits are read-only, and cannot be used for writing.
At initial reset, event counter 0 is set to "00H".
EV10–EV13: Event counter 1 low-order data (2FAH)
The four low-order data bits of event counter 1 are read out.
These four bits are read-only, and cannot be used for writing.
At initial reset, event counter 1 is set to "00H".
EV14–EV17: Event counter 1 high-order data (2FBH)
The four high-order data bits of event counter 1 are read out.
These four bits are read-only, and cannot be used for writing.
At initial reset, event counter 1 is set to "00H".
EV0RST: Event counter 0 reset (2FCHD0)
This is the register for resetting event counter 0.
When "1" is written : Event counter 0 reset
When "0" is written : No operation
Read-out : Always "0"
When "1" is written, event counter 0 is reset and the data becomes "00H". When "0" is written, no opera-
tion is executed.
This is a write-only bit, and is always "0" at read-out.
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