參數(shù)資料
型號: PI7C8150BNDIE
廠商: Pericom
文件頁數(shù): 96/109頁
文件大?。?/td> 0K
描述: IC PCI-PCI BRIDGE ASYNC 256-PBGA
標(biāo)準(zhǔn)包裝: 90
系列: *
應(yīng)用: *
接口: *
電源電壓: *
封裝/外殼: 256-BGA
供應(yīng)商設(shè)備封裝: 256-PBGA(17x17)
包裝: 管件
安裝類型: 表面貼裝
PI7C8150B
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 87 of 109
April 2009 – Revision 1.08
14.1.31
EXTENDED CHIP CONTROL REGISTER – OFFSET 48h
Bit
Function
Type
Description
0
Memory Read
Flow Through
Enable
R/W
Controls ability to do memory read flow through
0: Disable flow through during a memory read transaction
1: Enable flow through during a memory read transaction
Reset to 0
1
Park
R/W
Controls bus arbiter’s park function
0: Park to last master
1: Park to bridge
Reset to 0
15:2
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0
14.1.32
UPSTREAM MEMORY CONTROL REGISTER – OFFSET 48h
Bit
Function
Type
Description
16
Upstream (S to
P) Memory Base
and Limit Enable
R/W
0: Upstream memory is the entire range except the down stream
memory channel
1: Upstream memory is confined to upstream Memory Base and
Limit (See offset 50
th and 54th for upstream memory range)
Reset to 0
31:17
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0
14.1.33
SECONDARY BUS ARBITER PREEMPTION CONTROL
REGISTER – OFFSET 4Ch
Bit
Function
Type
Description
31:28
Secondary bus
arbiter
preemption
contorl
R/W
Controls the number of clock cycles after frame is asserted before
preemption is enabled.
1xxx: Preemption off
0000: Preemption enabled after 0 clock cycles
0001: Preemption enabled after 1 clock cycle
0010: Preemption enabled after 2 clock cycles
0011: Preemption enabled after 4 clock cycles
0100: Preemption enabled after 8 clock cycles
0101: Preemption enabled after 16 clock cycles
0110: Preemption enabled after 32 clock cycles
0111: Preemption enabled after 64 clock cycles
Reset to 0000
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