參數(shù)資料
型號(hào): PI7C8150BNDIE
廠商: Pericom
文件頁(yè)數(shù): 105/109頁(yè)
文件大小: 0K
描述: IC PCI-PCI BRIDGE ASYNC 256-PBGA
標(biāo)準(zhǔn)包裝: 90
系列: *
應(yīng)用: *
接口: *
電源電壓: *
封裝/外殼: 256-BGA
供應(yīng)商設(shè)備封裝: 256-PBGA(17x17)
包裝: 管件
安裝類(lèi)型: 表面貼裝
PI7C8150B
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 95 of 109
April 2009 – Revision 1.08
14.1.53
POWER MANAGEMENT DATA REGISTER – OFFSET E0h
Bit
Function
Type
Description
1:0
Power State
R/W
Indicates the current power state of PI7C8150B. If an
unimplemented power state is written to this register, PI7C8150B
completes the write transaction, ignores the write data, and does not
change the value of the field. Writing a value of D0 when the
previous state was D3 cause a chip reset without asserting
S_RESET_L
00: D0 state
01: not implemented
10: not implemented
11: D3 state
Reset to 0
7:2
Reserved
R/O
Read as 0
8
PME# Enable
R/O
Read as 0 as PI7C8150B does not support the PME# pin.
12:9
Data Select
R/O
Read as 0 as the data register is not implemented.
14:13
Data Scale
R/O
Read as 0 as the data register is not implemented.
15
PME status
R/O
Read as 0 as the PME# pin is not implemented.
14.1.54
CAPABILITY ID REGISTER – OFFSET E4h
Bit
Function
Type
Description
7:0
Capability ID
R/O
00h: Reserved.
01h: PCI Power Management (PCIPM)
02h: Accelerated Graphics Port (AGP)
03h: Vital Product Data (VPD)
04h: Slot Identification (SI)
05h: Message Signaled Interrupts (MSI)
06h: Compact PCI Hot Swap
07h-255h: Reserved
14.1.55
NEXT POINTER REGISTER – OFFSET E4h
Bit
Function
Type
Description
15:8
Next Pointer
R/O
End of pointer (00h)
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