參數(shù)資料
型號: PI7C8150BNDIE
廠商: Pericom
文件頁數(shù): 19/109頁
文件大?。?/td> 0K
描述: IC PCI-PCI BRIDGE ASYNC 256-PBGA
標(biāo)準(zhǔn)包裝: 90
系列: *
應(yīng)用: *
接口: *
電源電壓: *
封裝/外殼: 256-BGA
供應(yīng)商設(shè)備封裝: 256-PBGA(17x17)
包裝: 管件
安裝類型: 表面貼裝
PI7C8150B
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 17 of 109
April 2009 – Revision 1.08
CFG66 /
SCAN_EN_H /
CLK_RATE
125
K16
I
This is a multiplexed pin that has 3 functions (2 in
synchronous mode and 1 in asynchronous mode).
CFG66 - 66MHz Configuration (synchronous mode):
This pin is used to designate 66MHz operation. Tie
HIGH to enable 66MHz operation or tie LOW to
designate 33MHz operation.
SCAN_EN_H - Full-Scan Enable Control
(synchronous mode): When SCAN_EN_H is LOW,
full-scan is in shift operation. When SCAN_EN_H is
HIGH, full-scan is in parallel operation. Note: Valid only
in test mode. Pin is CFG66 in normal operation.
CLK_RATE – S_CLKOUT divider (asynchronous
mode): Determines the S_CLKOUT frequency relation
to ASYNC_CLK_IN.
0: S_SCLKOUT is half the frequency of
ASYNC_CLK_IN.
1: S_CLKOUT is the same frequency as
ASYNC_CLK_IN.
MS0, MS1
155, 106
B14, R16
I
Mode Selection: Selector for Asynchronous or
Synchronous mode.
MS0
MS1
Description
0
RESERVED
0
1
RESERVED
1
0
Synchronous Mode
1
Asynchronous Mode
2.2.5
GENERAL PURPOSE I/O INTERFACE SIGNALS
Name
Pin #
Type
Description
GPIO[3:0]
24, 25, 27, 28
J3, J2, J1, K1
TS
General Purpose I/O Data Pins: The 4 general-
purpose signals are programmable as either input-only
or bi-directional signals by writing the GPIO output
enable control register in the configuration space.
2.2.6
JTAG BOUNDARY SCAN SIGNALS
Name
Pin #
Type
Description
TCK
133
H15
I
Test Clock. Used to clock state information and data
into and out of the PI7C8150B during boundary scan.
TMS
132
H14
I
Test Mode Select. Used to control the state of the Test
Access Port controller.
TDO
130
H16
O
Test Data Output. Used as the serial output for the test
instructions and data from the test logic.
TDI
129
J15
I
Test Data Input. Serial input for the JTAG instructions
and test data.
TRST_L
134
G15
I
Test Reset. Active LOW signal to reset the Test Access
Port (TAP) controller into an initialized state.
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