參數(shù)資料
型號: PI7C8150BNDIE
廠商: Pericom
文件頁數(shù): 75/109頁
文件大?。?/td> 0K
描述: IC PCI-PCI BRIDGE ASYNC 256-PBGA
標(biāo)準(zhǔn)包裝: 90
系列: *
應(yīng)用: *
接口: *
電源電壓: *
封裝/外殼: 256-BGA
供應(yīng)商設(shè)備封裝: 256-PBGA(17x17)
包裝: 管件
安裝類型: 表面貼裝
PI7C8150B
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 68 of 109
April 2009 – Revision 1.08
To set asynchronous mode support, MS0 and MS1 must be configured accordingly:
MS0
MS1
Description
0
Reserved for future use
0
1
Reserved for future use
1
0
Synchronous Mode
1
Asynchronous Mode
When MS0 and MS1 are pulled to HIGH during the deassertion of P_RST, PI7C8150B
will go into asynchronous mode. The secondary clock outputs will then be derived from
ASYNC_CLKIN and not P_CLK. S_CLKOUT[9] is still connected to S_CLKIN to
provide the same timing as the bus clocks. CFG66/SCAN_EN_H becomes CLK_RATE in
asynchronous mode. Pulling CLK_RATE HIGH sets S_CLKOUT[9:0] equal to
ASYNC_CLKIN. Pulling CLK_RATE LOW sets S_CLKOUT[9:0] to half the frequency
of ASYNC_CLKIN. PI7C8150B will not be able to drive S_M66EN in asynchronous
mode.
10
GENERAL PURPOSE I/O INTERFACE
The PI7C8150B implements a 4-pin general purpose I/O interface. During normal
operation, device specific configuration registers control the GPIO interface. The GPIO
interface can be used for the following functions:
During secondary interface reset, the GPIO interface can be used to shift in a 16-bit
serial stream that serves as a secondary bus clock disable mask.
Along with the GPIO[3] pin, a live insertion bit can be used to bring the PI7C8150B to
a halt through hardware, permitting live insertion of option cards behind the
PI7C8150B.
10.1
GPIO CONTROL REGISTERS
During normal operation, the following device specific configuration registers control the
GPIO interface:
The GPIO output data register
The GPIO output enable control register
The GPIO input data register
These registers consist of five 8-bit fields:
Write-1-to-set output data field
Write-1-to-clear output data field
Write-1-to-set signal output enable control field
Write-1-to-clear signal output enable control field
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