參數(shù)資料
型號(hào): PI7C8150BNDIE
廠商: Pericom
文件頁(yè)數(shù): 87/109頁(yè)
文件大小: 0K
描述: IC PCI-PCI BRIDGE ASYNC 256-PBGA
標(biāo)準(zhǔn)包裝: 90
系列: *
應(yīng)用: *
接口: *
電源電壓: *
封裝/外殼: 256-BGA
供應(yīng)商設(shè)備封裝: 256-PBGA(17x17)
包裝: 管件
安裝類(lèi)型: 表面貼裝
PI7C8150B
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 79 of 109
April 2009 – Revision 1.08
Bit
Function
Type
Description
30
Signaled System
Error
R/WC
Set to 1 when P_SERR_L is asserted
Reset to 0
31
Detected Parity
Error
R/WC
Set to 1 when address or data parity error is detected on the primary
interface
Reset to 0
14.1.5
REVISION ID REGISTER – OFFSET 08h
Bit
Function
Type
Description
7:0
Revision
R/O
Indicates revision number of device. Hardwired to 02h
14.1.6
CLASS CODE REGISTER – OFFSET 08h
Bit
Function
Type
Description
15:8
Programming
Interface
R/O
Read as 0 to indicate no programming interfaces have been defined
for PCI-to-PCI bridges
23:16
Sub-Class Code
R/O
Read as 04h to indicate device is PCI-to-PCI bridge
31:24
Base Class Code
R/O
Read as 06h to indicate device is a bridge device
14.1.7
CACHE LINE SIZE REGISTER – OFFSET 0Ch
Bit
Function
Type
Description
7:0
Cache Line Size
R/W
Designates the cache line size for the system and is used when
terminating memory write and invalidate transactions and when
prefetching memory read transactions.
Only cache line sizes (in units of 4-byte) which are a power of two
are valid (only one bit can be set in this register; only 00h, 01h, 02h,
04h, 08h, and 10h are valid values).
Reset to 0
14.1.8
PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch
Bit
Function
Type
Description
15:8
Primary Latency
timer
R/W
This register sets the value for the Master Latency Timer, which
starts counting when the master asserts FRAME_L.
Reset to 0
14.1.9
HEADER TYPE REGISTER – OFFSET 0Ch
Bit
Function
Type
Description
23:16
Header Type
R/O
Read as 01h to indicate that the register layout conforms to the
standard PCI-to-PCI bridge layout.
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