參數資料
| 型號： | PI7C8150BNDIE |
| 廠商： | Pericom |
| 文件頁數： | 29/109頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 256-PBGA |
| 標準包裝： | 90 |
| 系列： | * |
| 應用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 256-BGA |
| 供應商設備封裝： | 256-PBGA（17x17） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C8150B
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 26 of 109
April 2009 – Revision 1.08
byte enable bits are compared. If any of the byte enable bits are turned off (driven HIGH),
the corresponding byte of write data is not compared.
If the initiator repeats the write transaction before the data has been transferred to the
target, PI7C8150B returns a target retry to the initiator. PI7C8150B continues to return a
target retry to the initiator until write data is delivered to the target, or until an error
condition is encountered. When the write transaction is repeated, PI7C8150B does not
make a new entry into the delayed transaction queue. Section 3.8.3.1 provides detailed
information about how PI7C8150B responds to target termination during delayed write
transactions.
PI7C8150B implements a discard timer that starts counting when the delayed write
completion is at the head of the delayed transaction completion queue.
The initial value of this timer can be set to the retry counter register offset 78h.
If the initiator does not repeat the delayed write transaction before the discard
timer expires, PI7C8150B discards the delayed write completion from the delayed
transaction completion queue. PI7C8150B also conditionally asserts P_SERR_L
(see Section 6.4).
3.5.4
WRITE TRANSACTION ADDRESS BOUNDARIES
PI7C8150B imposes internal address boundaries when accepting write data. The aligned
address boundaries are used to prevent PI7C8150B from continuing a transaction over a
device address boundary and to provide an upper limit on maximum latency. PI7C78150
returns a target disconnect to the initiator when it reaches the aligned address boundaries
under conditions shown in Table 3-3.
Table 3-3. Write Transaction Disconnect Address Boundaries
Type of Transaction
Condition
Aligned Address Boundary
Delayed Write
All
Disconnects after one data transfer
Posted Memory Write
Memory write disconnect control
bit = 0
(1)
4KB aligned address boundary
Posted Memory Write
Memory write disconnect control
bit = 1
(1)
Disconnects at cache line boundary
Posted Memory Write and
Invalidate
Cache line size
≠ 1, 2, 4, 8, 16
4KB aligned address boundary
Posted Memory Write and
Invalidate
Cache line size = 1, 2, 4, 8, 16
Cache line boundary if posted memory
write data FIFO does not have enough
space for the cache line
Note 1.
Memory write disconnect control bit is bit 1 of the chip control register at offset 40h in the
configuration space.
3.5.5
BUFFERING MULTIPLE WRITE TRANSACTIONS
PI7C8150B continues to accept posted memory write transactions as long as space for at
least one DWORD of data in the posted write data buffer remains. If the posted write data
buffer fills before the initiator terminates the write transaction, PI7C8150B returns a target
disconnect to the initiator.
Delayed write transactions are posted as long as at least one open entry in the delayed
transaction queue exists. Therefore, several posted and delayed write transactions can exist
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相關代理商/技術參數 |
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| PI7C8150BNDIE-33 | 功能描述:外圍驅動器與原件 - PCI 2 Port 32B PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8150DMAE | 功能描述:外圍驅動器與原件 - PCI 2-Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8150DND | 制造商:Pericom Semiconductor Corporation 功能描述:BRIDGE 制造商:Pericom Semiconductor Corporation 功能描述:2 PORT PCI BRIDGE - Rail/Tube |
| PI7C8150DNDE | 功能描述:外圍驅動器與原件 - PCI 2-Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8150EVB | 功能描述:界面開發(fā)工具 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
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