參數(shù)資料
型號： PI7C8150BNDIE
廠商： Pericom
文件頁數(shù)： 77/109頁
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE ASYNC 256-PBGA
標(biāo)準(zhǔn)包裝： 90
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 256-BGA
供應(yīng)商設(shè)備封裝： 256-PBGA（17x17）
包裝： 管件
安裝類型： 表面貼裝
PI7C8150B
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 7 of 109
April 2009 – Revision 1.08
13
SUPPORTED COMMANDS......................................................................................................... 73
13.1
PRIMARY INTERFACE ............................................................................................................. 73
13.2
SECONDARY INTERFACE....................................................................................................... 74
14
CONFIGURATION REGISTERS................................................................................................ 76
14.1
CONFIGURATION REGISTER ................................................................................................. 76
14.1.1
VENDOR ID REGISTER – OFFSET 00h......................................................................... 77
14.1.2
DEVICE ID REGISTER – OFFSET 00h .......................................................................... 77
14.1.3
COMMAND REGISTER – OFFSET 04h .......................................................................... 77
14.1.4
STATUS REGISTER – OFFSET 04h ................................................................................ 78
14.1.5
REVISION ID REGISTER – OFFSET 08h ...................................................................... 79
14.1.6
CLASS CODE REGISTER – OFFSET 08h....................................................................... 79
14.1.7
CACHE LINE SIZE REGISTER – OFFSET 0Ch ............................................................ 79
14.1.8
PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch ........................................... 79
14.1.9
HEADER TYPE REGISTER – OFFSET 0Ch................................................................... 79
14.1.10
PRIMARY BUS NUMBER REGISTSER – OFFSET 18h............................................ 80
14.1.11
SECONDARY BUS NUMBER REGISTER – OFFSET 18h ........................................ 80
14.1.12
SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h.................................... 80
14.1.13
SECONDARY LATENCY TIMER REGISTER – OFFSET 18h .................................. 80
14.1.14
I/O BASE REGISTER – OFFSET 1Ch.......................................................................... 80
14.1.15
I/O LIMIT REGISTER – OFFSET 1Ch ........................................................................ 81
14.1.16
SECONDARY STATUS REGISTER – OFFSET 1Ch................................................... 81
14.1.17
MEMORY BASE REGISTER – OFFSET 20h .............................................................. 82
14.1.18
MEMORY LIMIT REGISTER – OFFSET 20h............................................................. 82
14.1.19
PEFETCHABLE MEMORY BASE REGISTER – OFFSET 24h ................................ 82
14.1.20
PREFETCHABLE MEMORY LIMIT REGISTER – OFFSET 24h ............................ 82
14.1.21
PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER –
OFFSET 28h ....................................................................................................................................... 83
14.1.22
PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER –
OFFSET 2Ch....................................................................................................................................... 83
14.1.23
I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h .......................... 83
14.1.24
I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h......................... 83
14.1.25
ECP POINTER REGISTER – OFFSET 34h................................................................. 83
14.1.26
INTERRUPT LINE REGISTER – OFFSET 3Ch ......................................................... 83
14.1.27
INTERRUPT PIN REGISTER – OFFSET 3Ch............................................................ 84
14.1.28
BRIDGE CONTROL REGISTER – OFFSET 3Ch ....................................................... 84
14.1.29
DIAGNOSTIC / CHIP CONTROL REGISTER – OFFSET 40h.................................. 85
14.1.30
ARBITER CONTROL REGISTER – OFFSET 40h...................................................... 86
14.1.31
EXTENDED CHIP CONTROL REGISTER – OFFSET 48h....................................... 87
14.1.32
UPSTREAM MEMORY CONTROL REGISTER – OFFSET 48h ............................... 87
14.1.33
SECONDARY BUS ARBITER PREEMPTION CONTROL REGISTER – OFFSET
4Ch
.......................................................................................................................................... 87
14.1.34
UPSTREAM (S TO P) MEMORY BASE REGISTER – OFFSET 50h ........................ 88
14.1.35
UPSTREAM (S TO P) MEMORY LIMIT REGISTER – OFFSET 50h....................... 88
14.1.36
UPSTREAM (S TO P) MEMORY BASE UPPER 32-BITS REGISTER – OFFSET 54h
.......................................................................................................................................... 88
14.1.37
UPSTREAM (S TO P) MEMORY LIMIT UPPER 32-BITS REGISTER – OFFSET
58h
.......................................................................................................................................... 88
14.1.38
P_SERR_L EVENT DISABLE REGISTER – OFFSET 64h........................................ 88
14.1.39
GPIO DATA AND CONTROL REGISTER – OFFSET 64h ........................................ 90
14.1.40
SECONDARY CLOCK CONTROL REGISTER – OFFSET 68h ................................. 90
14.1.41
P_SERR_L STATUS REGISTER – OFFSET 68h ........................................................ 91
14.1.42
PORT OPTION REGISTER – OFFSET 74h ................................................................ 91
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