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參數(shù)資料
| 型號： | PI7C8150BNDIE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 30/109頁 |
| 文件大小： | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 256-PBGA |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 256-BGA |
| 供應(yīng)商設(shè)備封裝： | 256-PBGA（17x17） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C8150B
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 27 of 109
April 2009 – Revision 1.08
in data buffers at the same time. See Chapter 6 for information about how multiple posted
and delayed write transactions are ordered.
3.5.6
FAST BACK-TO-BACK TRANSACTIONS
PI7C8150B can recognize and post fast back-to-back write transactions.
When PI7C8150B cannot accept the second transaction because of buffer
space limitations, it returns a target retry to the initiator. The fast back-to-back enable bit
must be set in the command register for upstream write transactions, and in the bridge
control register for downstream write transactions.
3.6
READ TRANSACTIONS
Delayed read forwarding is used for all read transactions crossing PI7C8150B. Delayed
read transactions are treated as either prefetchable or non-prefetchable. Table 3-5 shows the
read behavior, prefetchable or non-prefetchable, for each type of read operation.
3.6.1
PREFETCHABLE READ TRANSACTIONS
A prefetchable read transaction is a read transaction where PI7C8150B performs
speculative DWORD reads, transferring data from the target before it is requested from the
initiator. This behavior allows a prefetchable read transaction to consist of multiple data
transfers. However, byte enable bits cannot be forwarded for all data phases as is done for
the single data phase of the non-prefetchable read transaction. For prefetchable read
transactions, PI7C8150B forces all byte enable bits to be turned on for all data phases.
Prefetchable behavior is used for memory read line and memory read multiple transactions,
as well as for memory read transactions that fall into prefetchable memory space.
The amount of data that is pre-fetched depends on the type of transaction. The amount of
pre-fetching may also be affected by the amount of free buffer space available in
PI7C8150B, and by any read address boundaries encountered.
Pre-fetching should not be used for those read transactions that have side effects in the
target device, that is, control and status registers, FIFO’s, and so on. The target device’s
base address register or registers indicate if a memory address region is prefetchable.
3.6.2
NON-PREFETCHABLE READ TRANSACTIONS
A non-prefetchable read transaction is a read transaction where PI7C8150B requests one
and only one DWORD from the target and disconnects the initiator after delivery of the
first DWORD of read data. Unlike prefetchable read transactions, PI7C8150B forwards the
read byte enable information for the data phase.
Non-prefetchable behavior is used for I/O and configuration read transactions, as well as
for memory read transactions that fall into non-prefetchable memory space.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8150BNDIE-33 | 功能描述:外圍驅(qū)動器與原件 - PCI 2 Port 32B PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8150DMAE | 功能描述:外圍驅(qū)動器與原件 - PCI 2-Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8150DND | 制造商:Pericom Semiconductor Corporation 功能描述:BRIDGE 制造商:Pericom Semiconductor Corporation 功能描述:2 PORT PCI BRIDGE - Rail/Tube |
| PI7C8150DNDE | 功能描述:外圍驅(qū)動器與原件 - PCI 2-Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8150EVB | 功能描述:界面開發(fā)工具 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
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