參數(shù)資料
型號: PI7C8150BNDIE
廠商: Pericom
文件頁數(shù): 84/109頁
文件大?。?/td> 0K
描述: IC PCI-PCI BRIDGE ASYNC 256-PBGA
標(biāo)準(zhǔn)包裝: 90
系列: *
應(yīng)用: *
接口: *
電源電壓: *
封裝/外殼: 256-BGA
供應(yīng)商設(shè)備封裝: 256-PBGA(17x17)
包裝: 管件
安裝類型: 表面貼裝
PI7C8150B
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 76 of 109
April 2009 – Revision 1.08
14
CONFIGURATION REGISTERS
PCI configuration defines a 64-byte space (configuration header) to define various
attributes of PI7C8150B as shown below.
14.1
CONFIGURATION REGISTER
31-24
23-16
15-8
7-0
Address
Device ID
Vendor ID
00h
Primary Status
Command
04h
Class Code
Revision ID
08h
Reserved
Header Type
Primary Latency Timer
Cache Line Size
0Ch
Reserved
10h
Reserved
14h
Secondary Latency
Timer
Subordinate Bus
Number
Secondary Bus
Number
Primary Bus Number
18h
Secondary Status
I/O Limit
I/O Base
1Ch
Memory Limit
Memory Base
20h
Prefetchable Memory Limit
Prefetchable Memory Base
24h
Prefetchable Base Upper 32-bit
28h
Prefetchable Limit Upper 32-bit
2Ch
I/O Limit Upper 16-bit
I/O Base Upper 16-bit
30h
Reserved
Capability Pointer to
DCh
34h
Reserved
38h
Bridge Control
Reserved
Interrupt Line
3Ch
Arbiter Control
Diagnostic / Chip Control
40h
Reserved
44h
Upstream Memory Control
Extended Chip Control
48h
Secondary
Bus Arbiter
Preemption
Control
Hot Swap Switch Time Slot
4Ch
Upstream (S to P) Memory Limit
Upstream (S to P) Memory Base
50h
Upstream (S to P) Memory Base Upper 32-bit
54h
Upstream (S to P) Memory Limit Upper 32-bit
58h
Reserved
5Ch
Reserved
60h
GPIO Data and Control
P_SERR# Event
Disable
64h
Reserved
P_SERR_L Status
Secondary Clock Control
68h
Reserved
6Ch
Reserved
70h
Reserved
Port Option
74h
Retry Counter
78h
Reserved
7Ch
Secondary Master Timeout Counter
Primary Master Timeout Counter
80h
Reserved
84h-AFh
Chassis Number
Slot Number
Next Pointer
Capability ID
B0h
Reserved
B4h-D8h
Power Management Capabilities
Next Item Pointer
Capability ID
DCh
Reserved
PPB Support Extensions
Power Management Data
E0h
Reserved
Next Pointer
Capability ID
E4h
Reserved
E8h-FFh
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