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參數(shù)資料
| 型號： | PI7C8150BNDIE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 80/109頁 |
| 文件大小： | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 256-PBGA |
| 標準包裝： | 90 |
| 系列： | * |
| 應用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 256-BGA |
| 供應商設備封裝： | 256-PBGA（17x17） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C8150B
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 72 of 109
April 2009 – Revision 1.08
Current Status
Next State
Action
D3cold
D0
Power-up reset. PI7C8150B performs the standard power-up reset
functions as described in Section 12.
PME# signals are routed from downstream devices around PCI-to-PCI bridges. PME#
signals do not pass through PCI-to-PCI bridges.
12
RESET
This chapter describes the primary interface, secondary interface, and chip reset
mechanisms.
12.1
PRIMARY INTERFACE RESET
PI7C8150B has a reset input, P_RESET_L. When P_RESET_L is asserted, the following
events occur:
PI7C8150B immediately tri-states all primary and secondary PCI interface signals.
PI7C8150B performs a chip reset.
Registers that have default values are reset.
P_RESET_L asserting and de-asserting edges can be asynchronous to P_CLK and
S_CLKOUT. PI7C8150B is not accessible during P_RESET_L. After P_RESET_L is de-
asserted, PI7C8150B remains inaccessible for 16 PCI clocks before the first configuration
transaction can be accepted.
12.2
SECONDARY INTERFACE RESET
PI7C8150B is responsible for driving the secondary bus reset signals, S_RESET_L.
PI7C8150B asserts S_RESET_L when any of the following conditions are met:
Signal P_RESET_L is asserted. Signal S_RESET_L remains asserted as long as
P_RESET_L is asserted and does not de-assert until P_RESET_L is de-asserted.
The secondary reset bit in the bridge control register is set. Signal S_RESET_L
remains asserted until a configuration write operation clears the secondary reset bit.
S_RESET_L pin is asserted. When S_RESET_L is asserted, PI7C8150B immediately 3-
states all the secondary PCI interface signals associated with the secondary port. The
S_RESET_L in asserting and de-asserting edges can be asynchronous to P_CLK.
When S_RESET_L is asserted, all secondary PCI interface control signals, including the
secondary grant outputs, are immediately 3-stated. Signals S1_AD, S1_CBE[3:0]#, S_PAR
are driven low for the duration of S_RESET_L assertion. All posted write and delayed
transaction data buffers are reset. Therefore, any transactions residing inside the buffers at
the time of secondary reset are discarded.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8150BNDIE-33 | 功能描述:外圍驅動器與原件 - PCI 2 Port 32B PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8150DMAE | 功能描述:外圍驅動器與原件 - PCI 2-Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8150DND | 制造商:Pericom Semiconductor Corporation 功能描述:BRIDGE 制造商:Pericom Semiconductor Corporation 功能描述:2 PORT PCI BRIDGE - Rail/Tube |
| PI7C8150DNDE | 功能描述:外圍驅動器與原件 - PCI 2-Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8150EVB | 功能描述:界面開發(fā)工具 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
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