14.1.43 RETRY COUNTER REGISTER " />
參數(shù)資料
型號(hào)： PI7C8150BNDIE
廠商： Pericom
文件頁(yè)數(shù)： 88/109頁(yè)
文件大小： 0K
描述： IC PCI-PCI BRIDGE ASYNC 256-PBGA
標(biāo)準(zhǔn)包裝： 90
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 256-BGA
供應(yīng)商設(shè)備封裝： 256-PBGA（17x17）
包裝： 管件
安裝類型： 表面貼裝
PI7C8150B
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 8 of 109
April 2009 – Revision 1.08
14.1.43
RETRY COUNTER REGISTER – OFFSET 78h .......................................................... 93
14.1.44
PRIMARY MASTER TIMEOUT COUNTER – OFFSET 80h ..................................... 93
14.1.45
SECONDARY MASTER TIMEOUT COUNTER – OFFSET 80h ............................... 93
14.1.46
CAPABILITY ID REGISTER – OFFSET B0h ............................................................. 93
14.1.47
NEXT POINTER REGISTER – OFFSET B0h ............................................................. 93
14.1.48
SLOT NUMBER REGISTER – OFFSET B0h .............................................................. 94
14.1.49
CHASSIS NUMBER REGISTER – OFFSET B0h ....................................................... 94
14.1.50
CAPABILITY ID REGISTER – OFFSET DCh............................................................. 94
14.1.51
NEXT ITEM POINTER REGISTER – OFFSET DCh ................................................. 94
14.1.52
POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET DCh ................. 94
14.1.53
POWER MANAGEMENT DATA REGISTER – OFFSET E0h................................... 95
14.1.54
CAPABILITY ID REGISTER – OFFSET E4h ............................................................. 95
14.1.55
NEXT POINTER REGISTER – OFFSET E4h ............................................................. 95
15
BRIDGE BEHAVIOR.................................................................................................................... 96
15.1
BRIDGE ACTIONS FOR VARIOUS CYCLE TYPES .............................................................. 96
15.2
ABNORMAL TERMINATION (INITIATED BY BRIDGE MASTER).................................... 96
15.2.1
MASTER ABORT................................................................................................................ 96
15.2.2
PARITY AND ERROR REPORTING ................................................................................ 96
15.2.3
REPORTING PARITY ERRORS ....................................................................................... 97
15.2.4
SECONDARY IDSEL MAPPING ...................................................................................... 97
16
IEEE 1149.1 COMPATIBLE JTAG CONTROLLER................................................................ 97
16.1
BOUNDARY SCAN ARCHITECTURE..................................................................................... 97
16.1.1
TAP PINS ............................................................................................................................ 98
16.1.2
INSTRUCTION REGISTER .............................................................................................. 98
16.2
BOUNDARY SCAN INSTRUCTION SET ................................................................................ 99
16.3
TAP TEST DATA REGISTERS................................................................................................ 100
16.4
BYPASS REGISTER .................................................................................................................100
16.5
BOUNDARY-SCAN REGISTER.............................................................................................. 100
16.6
TAP CONTROLLER ................................................................................................................. 100
17
ELECTRICAL AND TIMING SPECIFICATIONS ................................................................. 103
17.1
MAXIMUM RATINGS ............................................................................................................. 103
17.2
DC SPECIFICATIONS .............................................................................................................. 104
17.3
AC SPECIFICATIONS .............................................................................................................. 105
17.4
66MHZ TIMING........................................................................................................................ 105
17.5
33MHZ TIMING........................................................................................................................ 106
17.6
POWER CONSUMPTION ........................................................................................................ 106
18
PACKAGE INFORMATION...................................................................................................... 107
18.1
208-PIN FQFP PACKAGE DIAGRAM .................................................................................... 107
18.2
256-BALL PBGA PACKAGE DIAGRAM ............................................................................... 108
18.3
PART NUMBER ORDERING INFORMATION...................................................................... 108
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