參數(shù)資料
型號: PI7C8150BNDIE
廠商: Pericom
文件頁數(shù): 92/109頁
文件大小: 0K
描述: IC PCI-PCI BRIDGE ASYNC 256-PBGA
標(biāo)準(zhǔn)包裝: 90
系列: *
應(yīng)用: *
接口: *
電源電壓: *
封裝/外殼: 256-BGA
供應(yīng)商設(shè)備封裝: 256-PBGA(17x17)
包裝: 管件
安裝類型: 表面貼裝
PI7C8150B
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 83 of 109
April 2009 – Revision 1.08
14.1.21
PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS
REGISTER – OFFSET 28h
Bit
Function
Type
Description
31:0
Prefetchable
Memory Base
Address, Upper
32-bits [63:32]
R/W
Defines the upper 32-bits of a 64-bit bottom address of an address
range for the bridge to determine when to forward memory read and
write transactions from one interface to the other.
Reset to 0
14.1.22
PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS
REGISTER – OFFSET 2Ch
Bit
Function
Type
Description
31:0
Prefetchable
Memory Limit
Address, Upper
32-bits [63:32]
R/W
Defines the upper 32-bits of a 64-bit top address of an address range
for the bridge to determine when to forward memory read and write
transactions from one interface to the other.
Reset to 0
14.1.23
I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h
Bit
Function
Type
Description
15:0
I/O Base
Address, Upper
16-bits [31:16]
R/W
Defines the upper 16-bits of a 32-bit bottom address of an address
range for the bridge to determine when to forward I/O transactions
from one interface to the other.
Reset to 0
14.1.24
I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h
Bit
Function
Type
Description
31:0
I/O Limit
Address, Upper
16-bits [31:16]
R/W
Defines the upper 16-bits of a 32-bit top address of an address range
for the bridge to determine when to forward I/O transactions from
one interface to the other.
Reset to 0
14.1.25
ECP POINTER REGISTER – OFFSET 34h
Bit
Function
Type
Description
7:0
Enhanced
Capabilities Port
Pointer
R/O
Enhanced capabilities port offset pointer. Read as DCh to indicate
that the first item resides at that configuration offset.
14.1.26
INTERRUPT LINE REGISTER – OFFSET 3Ch
Bit
Function
Type
Description
7:0
Interrupt Line
R/W
For POST to program to FFh, indicating that the PI7C8150B does not
implement an interrupt pin.
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